Layout is a critical portion of good power supply design. See Figure 11-1 for a PCB layout example. The top layer contains the main power traces for PVIN, VIN, VOUT, and VPHASE. Also on the top layer are connections for several analog pins of the TPS54020 and a large area filled with PGND. The two internal layers are the same and contain mostly power planes, including PGND, VOUT, PVIN, and VPHASE. The bottom layer contains the remainder of the analog circuit connections, plus power planes similar to the internal layers. The top-side power and ground planes are connected to the bottom and internal power and ground planes with multiple vias placed around the board including several vias directly under the TPS54020 device to provide a thermal path from the top-side power planes to the other layer power planes. There are several signals paths that conduct fast changing currents or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supply performance.

To help eliminate these noise problems, the PVIN pin should be bypassed to ground with a low ESR ceramic bypass capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the PVIN pins, and the ground connections. The VIN pin must also be bypassed to ground using a low ESR ceramic capacitor with X5R or X7R dielectric. Make sure to connect this capacitor to the quiet analog ground trace rather than the power ground trace of the PVIn bypass capacitor. Because the PH connection is the switching node, the output inductor should be located close to the PH pin, and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The output filter capacitor ground should use the same power ground trace as the PVIN input bypass capacitor. Try to minimize this conductor length while maintaining adequate width. The small signal components should be grounded to the analog ground path as shown. The RT/CLK pin is sensitive to noise so the RT resistor should be located as close as possible to the IC and routed with minimal trace lengths. The additional external components can be placed approximately as shown. It may be possible to obtain acceptable performance with alternate PCB layouts, however this layout has been shown to produce good results and is meant as a guideline.

Land pattern and stencil information is provided in the data sheet addendum. The dimension and outline information is for the standard RUW package.