SLVSB10F July   2012  – November 2020 TPS54020

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings (1)
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Fixed Frequency PWM Control
      2. 8.3.2  Input Voltage and Power Input Voltage Pins (VIN and PVIN)
      3. 8.3.3  Voltage Reference (VREF)
      4. 8.3.4  Adjusting the Output Voltage
      5. 8.3.5  Safe Start-up into Prebiased Outputs
      6. 8.3.6  Error Amplifier
      7. 8.3.7  Slope Compensation
      8. 8.3.8  Enable and Adjusting Undervoltage Lockout
      9. 8.3.9  Adjustable Switching Frequency and Synchronization (RT/CLK)
      10. 8.3.10 Soft-Start (SS) Sequence
      11. 8.3.11 Power Good (PWRGD)
      12. 8.3.12 Bootstrap Voltage (BOOT) and Low Dropout Operation
      13. 8.3.13 Sequencing (SS)
      14. 8.3.14 Output Overvoltage Protection (OVP)
      15. 8.3.15 Overcurrent Protection
        1. 8.3.15.1 High-side MOSFET Overcurrent Protection
        2. 8.3.15.2 Low-side MOSFET Overcurrent Protection
      16. 8.3.16 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Single-Supply Operation
      2. 8.4.2 Split Rail Operation
      3. 8.4.3 Continuous Current Mode Operation (CCM)
      4. 8.4.4 Eco-mode Light-Load Efficiency Operation
      5. 8.4.5 Adjustable Switching Frequency (RT Mode)
      6. 8.4.6 Synchronization (CLK Mode)
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Small Signal Model for Loop Response
      2. 9.1.2 Simple Small Signal Model for Peak Current Mode Control
      3. 9.1.3 Small Signal Model for Frequency Compensation
      4. 9.1.4 Designing the Device Loop Compensation
        1. 9.1.4.1 Step One: Determine the Crossover Frequency (fC)
        2. 9.1.4.2 Step Two: Determine a Value for R6
        3. 9.1.4.3 Step Three: Calculate the Compensation Zero.
        4. 9.1.4.4 Step Four: Calculate the Compensation Noise Pole.
        5. 9.1.4.5 Step Five: Calculate the Compensation Phase Boost Zero.
      5. 9.1.5 Fast Transient Considerations
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Operating Frequency
        3. 9.2.2.3  Output Inductor Selection
        4. 9.2.2.4  Output Capacitor Selection
          1. 9.2.2.4.1 Response to a Load Transient
          2. 9.2.2.4.2 Output Voltage Ripple
          3. 9.2.2.4.3 Bus Capacitance
        5. 9.2.2.5  Input Capacitor Selection
        6. 9.2.2.6  Soft-Start Capacitor Selection
        7. 9.2.2.7  Bootstrap Capacitor Selection
        8. 9.2.2.8  Undervoltage Lockout Set Point
        9. 9.2.2.9  Output Voltage Feedback Resistor Selection
          1. 9.2.2.9.1 Minimum Output Voltage
        10. 9.2.2.10 Compensation Component Selection
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
        1. 12.1.1.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Support Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Electrical Characteristics

TJ = –40°C to +150°C, VIN = 4.5 V to 17 V, PVIN = 4.5 V to 17 V (unless otherwise noted)
PARAMETERCONDITIONSMINTYPMAXUNIT
SUPPLY VOLTAGE (VIN AND PVIN PINS)
PVIN operating input voltage1.617V
VIN operating input voltage4.517V
VIN internal UVLO thresholdVIN Rising44.5V
VIN internal UVLO hysteresis150mV
VIN shutdown supply currentVEN = 0 V210µA
VIN operating – nonswitching supply currentVVSENSE = 610 mV6001000µA
ENABLE AND UVLO (EN PIN)
VENEnable thresholdRising1.221.26V
Falling1.101.17V
IPInput current VEN below thresholdVEN = 1.1 V–1.15µA
IHAdded hysteresis current VEN above thresholdVEN = 1.3 V–3.3µA
VOLTAGE REFERENCE
VREFVoltage reference0 A ≤ IOUT ≤ 10 A, –40°C ≤ TA ≤ 150°C0.5940.60.606V
MOSFET
DRVHHigh-side switch resistanceBOOT-PH = 3 V9.518
BOOT-PH = 6 V(1)814
DRVLLow-side switch resistance(1)VVIN = 12 V611
ERROR AMPLIFIER
Error amplifier input bias currentVVIN = 12 V50nA
gMError amplifier transconductance–2 µA < ICOMP < 2 µA, VCOMP = 1 V1300µS
Error amplifier dc gainVVSENSE = 0.6 V3000V/V
Error amplifier source/sinkVCOMP = 1 V, 100 mV Overdrive±100µA
Start switching thresholdVCOMP0.27V
gMCOMP to ISWITCH transconductanceIILIM = NC20A/V
IILIM = RTN17
499 kΩ (1%) between ILIM and RTN13
CURRENT LIMIT
High-side switch current limit thresholdIILIM = NC13.415.116.5A
IILIM = RTN11.212.7514
High-side switch current limit threshold499 kΩ (1%) between ILIM and RTN8.39.410.2A
Low-side switch sourcing current limitIILIM = NC111315A
IILIM = RTN910.512
Low-side switch sourcing current limit499 kΩ (1%) between ILIM and RTN6.589.5A
Low-side switch sinking current limit–ve current denotes current sourced from PH pin–0.2–1.15A
Overcurrent protection scheme(HICCUP = RTN)Cycle-by-cycle
Hiccup delay before re-startHICCUP OPEN16384Cycles
Hiccup wait timeHICCUP OPEN128Cycles
THERMAL SHUTDOWN
Thermal shutdown175°C
Thermal shutdown hysteresis10°C
Thermal shutdown hiccup time16384Cycles
TIMING RESISTOR AND EXTERNAL CLOCK (RT/CLK PIN)
Switching frequencyRRT/CLK = 250 kΩ (1%)185205230kHz
RRT/CLK = 100 kΩ (1%)475500525
RRT/CLK = 50 kΩ (1%)8909901090
Minimum CLK pulse width20ns
RT/CLK high threshold2V
RT/CLK low threshold0.8V
RT/CLK falling edge to PH rising edge delayMeasure at 500 kHz with RT resistor in series66ns
PLL frequency range2001200kHz
SYNC_OUT (SYNC_OUT PIN)
Phase with RT/CLK180Degree
SYNC_OUT low threshold0.8V
SYNC_OUT high threshold2V
PH (PH PIN)
tON(min)Minimum on-timeMeasured at 90% to 90% of VIN, IPH = 2 A112165ns
IPH(LK)PH leakage currentVVIN = 17 V, VOUT = 0.6 V, TA = 150°C300µA
BOOT (BOOT PIN)
BOOT-PH UVLO2.13V
SOFT START AND TRACKING (SS/TR PIN)
ISSSoft-start charge current2.12.32.5µA
SS/TR to VSENSE matchingVSS/TR = 0.4 V2245mV
POWER GOOD (PWRGD PIN)
VSENSE thresholdVVSENSE falling (Fault)91%VREF
VVSENSE rising (Good)95
VVSENSE rising (Fault)108
VVSENSE falling (Good)104
Output high leakageVVSENSE = VREF, VPWRGD = 5.5 V3100nA
Output lowIPWRGD = 2 mA0.3V
Minimum input voltage for valid outputVPWRGD < 0.5 V at 100 µA0.61V
Minimum soft-start voltage for valid PWRGD1.4V
Measured at pins.