11.1 Layout Guidelines
The basic PCB board layout requires a separation of sensitive signal and power paths. If the layout is not carefully done, the regulator could suffer from the instability or noise problems.
The checklist below is suggested that be followed to get good performance for a well-designed board:
- Minimize the high current path including the switch FET, rectifier FET, and the output capacitor. This loop contains high di/dt switching currents ( nano seconds per ampere ) and easy to transduce the high frequency noise;
- Minimize the length and area of all traces connected to the SW pin, and always use a ground plane under the switching regulator to minimize inter plane coupling;
- Use a combination of bulk capacitors and smaller ceramic capacitors with low series resistance for the input and output capacitors. Place the smaller capacitors closer to the IC to provide a low impedance path for decoupling the noise;
- The ground area near the IC must provide adequate heat dissipating area. Connect the wide power bus (e.g., VOUT, SW, GND ) to the large area of copper, or to the bottom or internal layer ground plane, using vias for enhanced thermal dissipation;
- Place the input capacitor being close to the VIN pin and the PGND pin in order to reduce the input supply ripple;
- Place the noise sensitive network like the feedback and compensation being far away from the SW trace;
- Use a separate ground trace to connect the feedback, compensation, frequency set, and the current limit set circuitry. Connect this ground trace to the main power ground at a single point to minimize circulating currents.