9.2.4.4.2 Loop Compensation Design Steps
With the small signal models coming out, the next step is to calculate the compensation network parameters with the given inductor and output capacitance.
- Set the Cross Over Frequency, ƒ_{C}
- The first step is to set the loop crossover frequency, ƒ_{C}. The higher crossover frequency, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒ_{SW}, or 1/5 of the RHPZ frequency, ƒ_{RHPZ}. Then calculate the loop compensation network values of R_{C}, C_{C}, and C_{P} by following below equations.
- Set the Compensation Resistor, R_{C}
- By placing ƒ_{Z} below ƒ_{C}, for frequencies above ƒ_{C}, R_{C} | | R_{EA} ~= R_{C} and so R_{C} × G_{EA} sets the compensation gain. Setting the compensation gain, K_{COMP-dB}, at ƒ_{Z}, results in the total loop gain, T_{(s)} = G_{PS(s)} × H_{EA(s)} × He(s) being zero at ƒ_{C}.
- Therefore, to approximate a single-pole roll-off up to f_{P2}, rearrange Equation 22 to solve for RC so that the compensation gain, K_{EA}, at f_{C} is the negative of the gain, K_{PS}, read at frequency f_{C} for the power stage bode plot or more simply:
Equation 26.
where
- K_{EA } is gain of the error amplifier network
- K_{PS} is the gain of the power stage
- G_{EA} is the amplifier’s trans-conductance, the typical value of G_{EA} = 195 µA / V
- Set the compensation zero capacitor, C_{C}
- Place the compensation zero at the power stage R_{OUT} ,C_{OUT} pole’s position, so to get:
Equation 27.
- Set ƒ_{Z} = ƒ_{P}, and get the
Equation 28.
- Set the compensation pole capacitor, C_{P}
- Place the compensation pole at the zero produced by the R_{ESR} and the C_{OUT}, it is useful for canceling unhelpful effects of the ESR zero.
Equation 29.
Equation 30.
- Set ƒ_{P2} = ƒ_{ESR}, and get the
Equation 31.
- If the calculated value of C_{P} is less than 10 pF, it can be neglected.
Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output voltage ringing during the line and load transient. The R_{C} = 15 kΩ , C_{C} = 6.8 nF, C_{p} = 10 pF for this design example.