SLVSDA7E February   2017  – August 2019 TPS61178

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Under-voltage Lockout
      2. 8.3.2  Enable and Disable
      3. 8.3.3  Startup
      4. 8.3.4  Load Disconnect Gate Driver
      5. 8.3.5  Adjustable Peak Current Limit
      6. 8.3.6  Output Short Protection (with load disconnected FET)
      7. 8.3.7  Adjustable Switching Frequency
      8. 8.3.8  External Clock Synchronization (TPS611781)
      9. 8.3.9  Error Amplifier
      10. 8.3.10 Slope Compensation
      11. 8.3.11 Start-up with the Output Pre-Biased
      12. 8.3.12 Bootstrap Voltage (BST)
      13. 8.3.13 Over-voltage Protection
      14. 8.3.14 Thermal Shutdown
    4. 8.4 Device Functional Modes
      1. 8.4.1 Operation
      2. 8.4.2 Auto PFM Mode (TPS61178)
      3. 8.4.3 Forced PWM Mode (TPS611781)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Custom Design With WEBENCH® Tools
        2. 9.2.2.2 Setting the Switching Frequency
      3. 9.2.3 Setting the Current Limit
      4. 9.2.4 Setting the Output Voltage
        1. 9.2.4.1 Selecting the Inductor
        2. 9.2.4.2 Selecting the Output Capacitors
        3. 9.2.4.3 Selecting the Input Capacitors
        4. 9.2.4.4 Loop Stability and Compensation
          1. 9.2.4.4.1 Small Signal Model
          2. 9.2.4.4.2 Loop Compensation Design Steps
          3. 9.2.4.4.3 Selecting the Disconnect FET
          4. 9.2.4.4.4 Selecting the Bootstrap Capacitor
          5. 9.2.4.4.5 VCC Capacitor
      5. 9.2.5 TPS61178 Application Waveform
    3. 9.3 System Examples
      1. 9.3.1 TPS61178 with 14-V Output from 2.7-V to 4.4-V Input Voltage
      2. 9.3.2 TPS61178 Without Load Disconnect Function
      3. 9.3.3 TPS611781 External Clock Synchronization
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Development Support
        1. 12.1.2.1 Custom Design With WEBENCH® Tools
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Receiving Notification of Documentation Updates
    5. 12.5 Community Resources
    6. 12.6 Trademarks
    7. 12.7 Electrostatic Discharge Caution
    8. 12.8 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Loop Compensation Design Steps

With the small signal models coming out, the next step is to calculate the compensation network parameters with the given inductor and output capacitance.

  1. Set the Cross Over Frequency, ƒC
    • The first step is to set the loop crossover frequency, ƒC. The higher crossover frequency, the faster the loop response is. It is generally accepted that the loop gain cross over no higher than the lower of either 1/10 of the switching frequency, ƒSW, or 1/5 of the RHPZ frequency, ƒRHPZ. Then calculate the loop compensation network values of RC, CC, and CP by following below equations.
  2. Set the Compensation Resistor, RC
    • By placing ƒZ below ƒC, for frequencies above ƒC, RC | | REA ~= RC and so RC × GEA sets the compensation gain. Setting the compensation gain, KCOMP-dB, at ƒZ, results in the total loop gain, T(s) = GPS(s) × HEA(s) × He(s) being zero at ƒC.
    • Therefore, to approximate a single-pole roll-off up to fP2, rearrange Equation 22 to solve for RC so that the compensation gain, KEA, at fC is the negative of the gain, KPS, read at frequency fC for the power stage bode plot or more simply:
    • Equation 26. TPS61178 tps61178-equation-28.gif

      where

      • KEA is gain of the error amplifier network
      • KPS is the gain of the power stage
      • GEA is the amplifier’s trans-conductance, the typical value of GEA = 195 µA / V
  3. Set the compensation zero capacitor, CC
    • Place the compensation zero at the power stage ROUT ,COUT pole’s position, so to get:
    • Equation 27. TPS61178 tps61178-equation-29.gif
    • Set ƒZ = ƒP, and get the
    • Equation 28. TPS61178 tps61178-equation-30.gif
  4. Set the compensation pole capacitor, CP
    • Place the compensation pole at the zero produced by the RESR and the COUT, it is useful for canceling unhelpful effects of the ESR zero.
    • Equation 29. TPS61178 tps61178-equation-31.gif
      Equation 30. TPS61178 tps61178-equation-32.gif
    • Set ƒP2 = ƒESR, and get the
    • Equation 31. TPS61178 tps61178-equation-40.gif
    • If the calculated value of CP is less than 10 pF, it can be neglected.
    Designing the loop for greater than 45° of phase margin and greater than 6-dB gain margin eliminates output voltage ringing during the line and load transient. The RC = 15 kΩ , CC = 6.8 nF, Cp = 10 pF for this design example.