SLVSDA7E February 2017 – August 2019 TPS61178
The TPS61178x provides a gate driver to control an external FET to disconnect the output from the input at shutdown or output short conditions, shown in Figure 25.
The VDS, IDS and safe operation area (SOA) should be taken into consideration when selecting the FET:
For instance: VOUT = 16 V, ISHORT = 20 A , TSHORT = 30 µs.
SOA ≥ 4.8 mJ, VDS_DIS_MAX ≥ 16 V.
The CSD25404Q3 –20 V P-Channel NexFET™ Power FET is used for this design example.
An additional capacitor between the gate and source of the external FET is required to slow the turn-on speed.
Given 1.5 V threshold, CGS_PFET is 10 nF, the TON_PFET is around 300 µs.Please be aware that the maximum turn-on time should not exceed 3 ms, and the maximum capacitance CGS_PFET should be < 100 nF. Otherwise, the TPS61178x could not startup normally if the disconnect FET could not be turn on within the 3 ms.
The gate resistor depends on the gate-source voltage of the external FET,
Given the 5-V VGATE, the RGATE = 100 kΩ