SLVSFJ3C May   2022  – October 2023 TPS62870-Q1 , TPS62871-Q1 , TPS62872-Q1 , TPS62873-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Description (continued)
  7. 6 Device Options
  8. 7 Pin Configuration and Functions
  9. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 I2C Interface Timing Characteristics
    7. 8.7 Timing Requirements
    8. 8.8 Typical Characteristics
  10. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  Fixed-Frequency DCS Control Topology
      2. 9.3.2  Forced PWM and Power Save Modes
      3. 9.3.3  Precise Enable
      4. 9.3.4  Start-Up
      5. 9.3.5  Switching Frequency Selection
      6. 9.3.6  Output Voltage Setting
        1. 9.3.6.1 Output Voltage Range
        2. 9.3.6.2 Output Voltage Setpoint
        3. 9.3.6.3 Non-Default Output Voltage Setpoint
        4. 9.3.6.4 Dynamic Voltage Scaling
      7. 9.3.7  Compensation (COMP)
      8. 9.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 9.3.9  Spread Spectrum Clocking (SSC)
      10. 9.3.10 Output Discharge
      11. 9.3.11 Undervoltage Lockout (UVLO)
      12. 9.3.12 Overvoltage Lockout (OVLO)
      13. 9.3.13 Overcurrent Protection
        1. 9.3.13.1 Cycle-by-Cycle Current Limiting
        2. 9.3.13.2 Hiccup Mode
        3. 9.3.13.3 Current Limit Mode
      14. 9.3.14 Power Good (PG)
        1. 9.3.14.1 Standalone or Primary Device Behavior
        2. 9.3.14.2 Secondary Device Behavior
      15. 9.3.15 Remote Sense
      16. 9.3.16 Thermal Warning and Shutdown
      17. 9.3.17 Stacked Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-On Reset
      2. 9.4.2 Undervoltage Lockout
      3. 9.4.3 Standby
      4. 9.4.4 On
    5. 9.5 Programming
      1. 9.5.1 Serial Interface Description
      2. 9.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 9.5.3 I2C Update Sequence
      4. 9.5.4 I2C Register Reset
    6. 9.6 Register Map
  11. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Selecting the Inductor
        2. 10.2.2.2 Selecting the Input Capacitors
        3. 10.2.2.3 Selecting the Compensation Resistor
        4. 10.2.2.4 Selecting the Output Capacitors
        5. 10.2.2.5 Selecting the Compensation Capacitor, CC
        6. 10.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 10.2.3 Application Curves
    3. 10.3 Best Design Practices
    4. 10.4 Power Supply Recommendations
    5. 10.5 Layout
      1. 10.5.1 Layout Guidelines
      2. 10.5.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Support Resources
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Pin Configuration and Functions


GUID-20200713-CA0I-1TXD-LW2H-QHST1HM86FD6-low.svg
Figure 7-1 16-Pin RXS VQFN Package (Top View)
Table 7-1 Pin Functions
PinType(1)Description
NameNo.
COMP1—Device compensation input. A resistor and capacitor from this pin to GOSNS define the compensation of the control loop.
In stacked operation, connect the COMP pins of all stacked devices together and connect a resistor and capacitor between the common COMP node and GOSNS.
GOSNS2IOutput ground sense (differential output voltage sensing)
VOSNS3IOutput voltage sense (differential output voltage sensing)
EN4IThis is the enable pin of the device. The user must connect to this pin using a series resistor of at least 15 kΩ. A low logic level on this pin disables the device and a high logic level on this pin enables the device. Do not leave this pin unconnected.
For stacked operation, interconnect EN pins of all stacked devices with a resistor to the supply voltage or a GPIO of a processor. See Section 9.3.17 for a detailed description.
VIN5, 9PPower supply input. Connect the input capacitor as close as possible between VIN and GND.
GND6, 8GNDGround pin
SW7OThis pin is the switch pin of the converter and is connected to the internal power MOSFETs.
PG10I/OOpen-drain power-good output. Low impedance when not "power good," high impedance when "power good." This pin can be left open or be tied to GND when not used in single device operation.
In stacked operation, interconnect the PG pins of all stacked devices. Only the PG pin of the primary converter in stacked operation is an open-drain output. For devices that are defined as secondary converters in stacked mode, this pin is an input pin. See Section 9.3.17 for a detailed description.
MODE/SYNC11IThe device runs in power save mode when this pin is pulled low. If the pin is pulled high, the device runs in forced-PWM mode. If unused, this pin can be left floating and an internal pulldown resistor will pull it low. The mode pin can also be used to synchronize the device to an external clock.
SDA12I/OI2C serial data pin. Do not leave floating. Connect a pullup resistor to a logic high level.
Connect to GND for secondary devices in stacked operation and for device variants without I2C.
SCL13I/OI2C serial clock pin. Do not leave this pin floating. Connect a pullup resistor to a logic high level.
Connect this pin to GND for secondary devices in stacked operation and for device variants without I2C.
SYNC_OUT14OInternal clock output pin for synchronization in stacked mode. Leave this pin floating for single device operation. Connect this pin to the MODE/SYNC pin of the next device in the daisy-chain in stacked operation. Do not use this pin to connect to a non-TPS6287x-Q1 device.
During start-up, this pin is used to identify if a device must operate as a secondary converter in stacked operation. Connect a 47-kΩ resistor from this pin to GND to define a secondary converter in stacked operation. See Section 9.3.17 for a detailed description.
VSEL15—Start-up output voltage select pin. A resistor or short circuit to GND or VIN defines the selected output voltage. See Section 9.3.6.2.
FSEL16—Frequency select pin. A resistor or a short circuit to GND or VIN determines the free-running switching frequency. See Section 9.3.6.2.
Exposed Thermal Pad—The thermal pad must be soldered to GND to achieve an appropriate thermal resistance and for mechanical stability.
(1) I = input, O = output, P = power, GND = ground