SLVSGC5E January   2023  – October 2025 TPS62870 , TPS62871 , TPS62872 , TPS62873

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Range
        2. 7.3.6.2 Output Voltage Setpoint
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Standalone or Primary Device Behavior
        2. 7.3.14.2 Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Inductor
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CC
        6. 9.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.2 Forced PWM and Power Save Modes

The device can control the inductor current in three different ways to regulate the output:

  • Pulse-width modulation with continuous inductor current (PWM-CCM)
  • Pulse-width modulation with discontinuous inductor current (PWM-DCM)
  • Pulse-frequency modulation with discontinuous inductor current and pulse skipping (PFM-DCM)

The on-time in PWM-CCM is set by Equation 1. For very small output voltages, a minimum on time (ton, min) of approximately 50ns reduces the switching frequency from the set value. Even when the minimum on-time is reached, the device maintains proper output voltage regulation by extending the off-time.

Equation 1. tON=VOUTVIN× fSW

During PWM-CCM operation, the device switches at a constant frequency and the inductor current is continuous (see Figure 7-2). PWM operation achieves the lowest output voltage ripple and the best transient performance.


TPS62870 TPS62871 TPS62872 TPS62873 Continuous Conduction Mode (PWM-CCM) Current Waveform

Figure 7-2 Continuous Conduction Mode (PWM-CCM) Current Waveform

During PWM-DCM operation, the device switches at a constant frequency and the inductor current is discontinuous (see Figure 7-3). In this mode, the device controls the peak inductor current to maintain the selected switching frequency while still being able to regulate the output.

Use Equation 2 to calculate the output current threshold at which the device enters PWM-DCM.

Equation 2. IOUT(CCM-DCM)=VIN–VOUT2LtON

with tON according Equation 1.


TPS62870 TPS62871 TPS62872 TPS62873 Discontinuous Conduction Mode (PWM-DCM) Current Waveform

Figure 7-3 Discontinuous Conduction Mode (PWM-DCM) Current Waveform

During PFM-DCM operation, the device keeps the peak inductor current constant (at a level corresponding to the minimum on time of the converter) and skips pulses to regulate the output (see Figure 7-4). The switching pulses that occur during PFM-DCM operation are synchronized to the internal clock.

TPS62870 TPS62871 TPS62872 TPS62873 Discontinuous Conduction Mode (PFM-DCM) Current WaveformFigure 7-4 Discontinuous Conduction Mode (PFM-DCM) Current Waveform

Use Equation 3 to calculate the output current threshold at which the device changes from PWM-DCM to PFM-DCM:

Equation 3. IOUT(PFM-DCM)=VIN×tON_min_PFM2× 1-VOUTVINL

with tON_min_PFM being the minimum on time in PFM-DCM of approximately 20ns.

Figure 7-5 shows how this threshold typically varies with VIN and VOUT for a switching frequency of 2.25MHz.

TPS62870 TPS62871 TPS62872 TPS62873 Output Current PFM-DCM Entry ThresholdFigure 7-5 Output Current PFM-DCM Entry Threshold
The user can configure the device to use either forced PWM (FPWM) mode or power save mode (PSM):
  • In forced PWM mode, the device uses PWM-CCM at all times.
  • In power save mode, the device uses PWM-CCM at medium and high loads, PWM-DCM at low loads, and PFM-DCM at very low loads. The transition between the different operating modes is seamless.

Table 7-1 shows the function table of the MODE/SYNC pin and the FPWMEN bit in the CONTROL1 register, which control the operating mode of the device.

Table 7-1 FPWM Mode and Power-Save Mode Selection
MODE/SYNC PINFPWMEN BITOPERATING MODEREMARK
Low0PSMDo not use in a stacked configuration.
1FPWM
HighXFPWM
Sync ClockXFPWM