SLVSGC5E January   2023  – October 2025 TPS62870 , TPS62871 , TPS62872 , TPS62873

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Options
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 I2C Interface Timing Characteristics
    7. 6.7 Timing Requirements
    8. 6.8 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Fixed-Frequency DCS-Control Topology
      2. 7.3.2  Forced PWM and Power Save Modes
      3. 7.3.3  Precise Enable
      4. 7.3.4  Start-Up
      5. 7.3.5  Switching Frequency Selection
      6. 7.3.6  Output Voltage Setting
        1. 7.3.6.1 Output Voltage Range
        2. 7.3.6.2 Output Voltage Setpoint
        3. 7.3.6.3 Non-Default Output Voltage Setpoint
        4. 7.3.6.4 Dynamic Voltage Scaling
      7. 7.3.7  Compensation (COMP)
      8. 7.3.8  Mode Selection and Clock Synchronization (MODE/SYNC)
      9. 7.3.9  Spread Spectrum Clocking (SSC)
      10. 7.3.10 Output Discharge
      11. 7.3.11 Undervoltage Lockout (UVLO)
      12. 7.3.12 Overvoltage Lockout (OVLO)
      13. 7.3.13 Overcurrent Protection
        1. 7.3.13.1 Cycle-by-Cycle Current Limiting
        2. 7.3.13.2 Hiccup Mode
        3. 7.3.13.3 Current Limit Mode
      14. 7.3.14 Power Good (PG)
        1. 7.3.14.1 Standalone or Primary Device Behavior
        2. 7.3.14.2 Secondary Device Behavior
      15. 7.3.15 Remote Sense
      16. 7.3.16 Thermal Warning and Shutdown
      17. 7.3.17 Stacked Operation
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power-On Reset
      2. 7.4.2 Undervoltage Lockout
      3. 7.4.3 Standby
      4. 7.4.4 On
    5. 7.5 Programming
      1. 7.5.1 Serial Interface Description
      2. 7.5.2 Standard, Fast, Fast Mode Plus Protocol
      3. 7.5.3 I2C Update Sequence
      4. 7.5.4 I2C Register Reset
  9. 8 Register Map
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Selecting the Inductor
        2. 9.2.2.2 Selecting the Input Capacitors
        3. 9.2.2.3 Selecting the Compensation Resistor
        4. 9.2.2.4 Selecting the Output Capacitors
        5. 9.2.2.5 Selecting the Compensation Capacitor, CC
        6. 9.2.2.6 Selecting the Compensation Capacitor, CC2
      3. 9.2.3 Application Curves
    3. 9.3 Best Design Practices
    4. 9.4 Power Supply Recommendations
    5. 9.5 Layout
      1. 9.5.1 Layout Guidelines
      2. 9.5.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Third-Party Products Disclaimer
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.3.14.1 Standalone or Primary Device Behavior

The primary purpose of the PG pin is to indicate if the output voltage is in regulation, but the PG pin also indicates if the device is in thermal shutdown or disabled. Table 7-7 summarizes the behavior of the PG pin in a standalone or primary device.

Table 7-7 Power-Good Function Table
VIN EN VOUT SOFT START PGBLNKDVS TJ PG
VIN < 2V X X X X X Undefined
VIT-(UVLO) ≥ VIN ≥ 2V X X X X X Low
VIT-(OVLO) > VIN > VIT+(UVLO) L X X X X Low
H X Active X X Low
VOUT > VT+(OVP) or VOUT < VT-(UVP) Inactive 0 X Low
1
(DVS inactive)		 X Low
X 1
(DVS active)		 TJ < TSD Hi-Z
VT-(OVP) > VOUT > VT+(UVP) X Hi-Z
X X X TJ > TSD Low
VIN > VIT+(OVLO) X X X X X Low

Figure 7-13 shows a functional block diagram of the power-good function in a standalone or primary device. A window comparator monitors the output voltage, and the output of the comparator goes high if the output voltage is either less than 95% (typical) or greater than 105% (typical) of the nominal output voltage. The output of the window comparator is deglitched – the typical deglitch time is 40µs – and then used to drive the open-drain PG pin.


TPS62870 TPS62871 TPS62872 TPS62873 Power-Good Functional Block Diagram (Standalone or Primary Device)
Figure 7-13 Power-Good Functional Block Diagram (Standalone or Primary Device)

If an output under or overvoltage event occurs, the device sets the PBUV or PBOV bits in the STATUS register, respectively. The device clears the PBOV and PBUV bits if the user reads the STATUS register after the power-bad condition no longer exists.

During DVS activity, the voltage reference for the window comparator follows the ramping output voltage setpoint. During a DVS in FPWM mode, PG normally does not go low because the device actively drives the output voltage up or down to follow the DVS ramp. In power save mode, PG can go low on the ramp down, if there is not sufficient load to pull down the output voltage fast enough to remain within the limits of the window comparator. In both FPWM and power save mode, setting PGBLNKDVS = 1 in the CONTROL3 register forces the device to ignore the output of the power-good window comparator for the duration of the DVS ramping time (as set by the VRAMP[1:0] bits in the CONTROL1 register), keeping the PG pin high-impedance. After the DVS time has passed, PG again reflects the output of the window comparator.

Note that the PG pin is always low, regardless of the output of the window comparator, when:

  • The device is in thermal shutdown
  • The device is disabled
  • The device is in undervoltage lockout or overvoltage lockout (UVLO or OVLO)
  • The device is in soft start

A small RC filter (1kΩ + 10pF, for example) can be added to the PG pin to filter out high frequency signals.