SLVSF11 June 2019 TPS652170
PRODUCTION DATA.
Refer to the PDF data sheet for device specific package drawings
DEFPG is shown in Figure 43 and described in Table 15.
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This register is password protected.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Reserved | LDO1PGM | LDO2PGM | PGDLY[1:0] | ||||
R-0000b | R/W-1b | R/W-1b | R/W-00b |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7–4 | Reserved | R | 0000b | These bits are reserved |
3 | LDO1PGM | R/W, E2 | 1b |
LDO1 power-good masking bit 0b = PGOOD pin is pulled low if LDO1_PG is low 1b = LDO1_PG status does not affect the status of the PGOOD output pin. |
2 | LDO2PGM | R/W, E2 | 1b |
LDO2 power-good masking bit 0b = PGOOD pin is pulled low if LDO2_PG is low 1b = LDO2_PG status does not affect the status of the PGOOD output pin. |
1–0 | PGDLY[1:0] | R/W, E2 | 00b |
Power-good delay
00b = 20 ms 01b = 100 ms 10b = 200 ms 11b = 400 ms |