SLVSCQ9E Data sheet

SLVSCQ9E November 2014 – March 2022 TPS65400

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

RGZ|48
- MPQF123F

Thermal pad, mechanical data (Package|Pins)

RGZ|48
- QFND014T

Orderable Information

8.3.1.1 Startup Timing

Figure 8-3 shows the startup timing of the TPS65400. Upon power-up or the rising edge of CE, the internal power rails VDDA, VDDG, and VDDD startup during the time labeled t_start. Following t_start, a delay of t₁ follows (which is defined by the user through the timing of RST_N). During time t_start and t₁, the COMP terminal is internally discharged through a 2-kΩ resistor. At the rising edge of RST_N, the TPS65400 begins two actions:

The TPS65400 begins its precharge of the COMP terminal (indicated by t_precharge). The length of t_precharge needed to precharge the COMP terminal depends on the time constant of the R and C components. The internal precharge voltage source remains on even during normal operation, preventing the COMP terminal from falling below 0.6 V except during faults (OVP, OCP, and so forth).
The TPS65400 begins its configuration sequence (indicated by t_config), and loads parameters from the EEPROM. Parameters to be set include Vout, switching frequency, soft-start timing, and current limit.

After t_config is complete, t_{reset_delay} begins. The length of t_{reset_delay} is user-configurable through PMBus register DCh. After t_{reset_delay} is complete, the TPS65400 begins its startup sequence. The startup sequence is EEPROM-configurable, so any of the four switchers could be the first to startup with a configurable delay. In this particular example, SW1 is configured to startup first after a delay of t_{SW1_TON_DELAY}, which is configurable through PMBus register (DDh) TON_TOFF_DELAY.

PGOOD1 and ENSW2 are tied together externally, and t_{ON_DELAY1} and t_{ON_DELAY2} are configured through PMBus.

Figure 8-3 Timing Showing Startup from CE

To summarize, the length of time from rising edge of CE to soft-start of the first switcher in the sequence is:

Equation 1. t_{CE_to_SS} = t_start + t₁ + t_config + t_{reset_delay} + t₂ + t_{SW1_ON_DELAY}

The delays, t_{reset_delay} and t_{SW1_ON_DELAY}, are both configurable through PMBus. The delay, t_config, is typically 1.1 ms. The delays, t₁ and t₂, are determined by the user-defined timing of RST_N and ENSW1. They can both be set to 0 by pulling RST_N high before the end of t_start and ENSW1 high before the end of t_{reset_delay}. One simple way to do this would be to tie both signals to VDDD.