TPS65400

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4.5 V to 18 V input, 4 A / 4 A / 2 A / 2 A synchronous quad converter with PMBus/I2C interface

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Product details

Parameters

Vin (Min) (V) 4.5 Vin (Max) (V) 18 Vout (Min) (V) 0.8 Vout (Max) (V) 16 Iout (Max) (A) 4 Iq (Typ) (mA) 8 Switching frequency (Min) (kHz) 275 Switching frequency (Max) (kHz) 2200 Features Adjustable Current Limit, Enable, Frequency Synchronization, Light Load Efficiency, I2C/PMBus, Phase Interleaving, Power Good, Pre-Bias Start-Up, Synchronous Rectification, UVLO Adjustable, Adaptive/Dynamic Voltage Scaling, Soft Start Adjustable Operating temperature range (C) -40 to 85 Rating Catalog Regulated outputs (#) 4 open-in-new Find other Buck converters (integrated switch)

Package | Pins | Size

VQFN (RGZ) 48 49 mm² 7 x 7 open-in-new Find other Buck converters (integrated switch)

Features

  • Efficiency up to 95% for Each Switching Regulator
  • Switching Regulator Specifications:
    • Input Voltage Range: 4.5 to 18 V
    • Vout Range: 0.6 V-90%Vin
    • SW1, SW2 Iout: 4-A Max
    • SW3, SW4 Iout: 2-A Max
  • Pre-Bias Startup Algorithm Minimizes Voltage Dip During Startup
  • Internal Undervoltage Lockout (UVLO), Overcurrent Protection (OCP), Overvoltage Protection (OVP), and Overtemperature Protection (OTP)
  • AECQ-100 Grade 1 Option
  • Thermally-Enhanced 7-mm × 7-mm 48-Pin, 0.5-mm Pitch VQFN Package
  • Pin Accessible Features:
    • Adjustable VOUT With External Feedback Resistors
    • Sequencing Control Through Precision Enable Pins for Each Switcher
    • Resistor Adjustable PWM Switching Frequency from 275 kHz to 2.2 MHz
    • Clock Sync Input and Clock Output
    • Soft-Start Delay Through External Capacitor
    • Current Sharing Between SW1 and SW2 and Between SW3 and SW4 Allows Support of Higher Current Needs if Required
  • PMBus Runtime Control and Status
    • Runtime Voltage Positioning Through Adjustment of VREF
    • Enable and Disable of Each Switcher
    • Fault and Status Monitoring
  • User-Configurable PMBus / I2C Options, Saved in EEPROM
    • Power Supply Turn-On and Turn-Off Sequencing
    • Sequencing can be Based on Fixed Time Delays or PGOOD Dependence
    • Initial Voltage Positioning Through VREF Configuration
    • PWM Frequency Adjustment for Each Switcher
    • Individual PWM Phase Alignment for Each Switcher to Minimize Ripple and Capacitor Size
    • Adjustable Current Limit on Each Regulator Enables Size and Cost Optimization of Inductors
    • Soft-Start Time

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Description

The TPS65400 is an integrated PMU optimized for applications requiring small form factor and high power conversion efficiency, enabling small space-constrained equipment with high ambient operating temperature without cooling. It provides high-power efficiency at a system level by enabling a single stage conversion from an intermediate distribution bus with an optimized combination of regulators.

TPS65400 implements a PMBus-I2C-compatible digital interface. It helps Core Chip optimize system performance by runtime changing regulated voltage, power sequence, phase interleaving, operating frequency, read back operating status, and so forth.

The TPS65400 consists of four high-current buck switching regulators (SW1, SW2, SW3, and SW4) with integrated FETs. The switching power supplies are intended for powering high-current digital circuits such as the processor, FPGA, ASIC, memory, and digital I/Os. SW1 and SW2 support 4 A each, and SW3 and SW4 support 2 A each. Each regulator’s switching frequency is independently adjustable up to 2.2 MHz.

Current limit programmability on each switcher enables optimization of inductor ratings for a particular application configuration not requiring the maximum current capability.

The TPS65400 can be powered from a single-input voltage rail between 4.5 and 18 V, making it suitable for applications running off a 5- or 12-V intermediate power distribution bus.

Sequencing requirements can be met using the individual enable terminals or by programming the sequence through the I2C bus into the onboard EEPROM. Output voltages can be set through external resistor networks and VREF can be programmed from 0.6 to 1.87 V in 10-mV steps. All control and status info can be accessed through a PMBus-compatible I2C bus.

The TPS65400 provides a high level of flexibility for monitoring and control through the I2C bus while providing the option of programmability through the use of external components and voltage levels for systems not using I2C.

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Technical documentation

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Type Title Date
* Datasheet TPS65400 4.5- to 18-V Input Flexible Power Management Unit With PMBus/I2C Interface datasheet (Rev. D) Jul. 19, 2018
Application notes How to Calculate the Load Pole and ESR Zero When Using Hybrid Output Capacitors (Rev. A) Apr. 02, 2019
Technical articles Minimize the impact of the MLCC shortage on your power application Mar. 29, 2019
Technical articles Which power supply sequencing solution is right for you? Mar. 30, 2015
User guides TPS65400 EVM User’s Guide Oct. 27, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$199.00
Description

The TPS65400EVM-678 evaluation module (EVM) is a fully assembled and tested circuit for evaluating the TPS65400. The max DC output current of this EVM is 4A,4A, 2A and 2A. The EVM contains input and output connectors as well as control jumpers to ease evaluation of device features. It also has EN1 (...)

Features

  • Wide Input Voltage Range 4.5V to 18V and Integrated Dual Buck Converter, Maximum Continuous Current 4A (Buck1 )/2A (Buck2)
  • Adjustable Switching frequency 200KHz-2.2MHz and have External Clock Synchronization
  • PMBus/I2C interface for dynamic voltage scaling, phase shift, power sequence

GUIS FOR EVALUATION MODULES (EVM) Download
SLVC603.ZIP (12992 KB)

Software development

DRIVERS & LIBRARIES Download
SLVC604.ZIP (238968 KB)

Design tools & simulation

SIMULATION MODELS Download
SLVMAI5.ZIP (73 KB) - PSpice Model
SIMULATION MODELS Download
SLVMAI6.ZIP (91 KB) - PSpice Model
SIMULATION MODELS Download
SLVMC03.TSC (139 KB) - TINA-TI Reference Design
SIMULATION MODELS Download
SLVMC04.ZIP (19 KB) - TINA-TI Spice Model

Reference designs

REFERENCE DESIGNS Download
Wideband Receiver Design Using 66AK2L06 JESD204B Attach to ADC32RF80 Reference Design
TIDEP0081 — For wideband receiver system developers currently using FPGA or ASIC to connect High Speed data converters to a baseband processor, who need faster time to market with increased performance and significant reduction in cost, power, and size. This reference design includes the first widely available (...)
document-generic Schematic document-generic User guide
REFERENCE DESIGNS Download
Compact Digital Quad 4/4/2/2A Point-of-load Reference Design for Space Constrained Applications
PMP11414 The PMP11414 reference design features TPS65400 quad 4/4/2/2A output point-of-load in a tiny 0.65"x0.875" solution size (16.5mmx22.2mm). TPS65400 fully integrates four buck regulators into a small 7mmx7mm QFN package. It also has PMBus capability for flexible control and configuration.  The (...)
document-generic Schematic document-generic User guide

CAD/CAE symbols

Package Pins Download
VQFN (RGZ) 48 View options

Ordering & quality

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