The first step when designing with a linear regulator is to examine the maximum load current along with the input and output voltage requirements to determine if the device thermal and dropout voltage requirements can be met. At 0.4A, the dropout voltage of the TPS73633 is a maximum of 200mV over temperature; thus, the dropout headroom is sufficient for operation over both input and output voltage accuracy.

The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass transistor from the input to the output times the maximum load current. In this example, the maximum voltage drop across in the pass transistor is 5V + 3% (5.15V) minus 3.3V – 1% (3.267V) or 1.883V. The power dissipated in the pass transistor is calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum power dissipated in the linear regulator is 942mW. Once the power dissipated in the linear regulator is known, the corresponding junction temperature rise can be calculated. To calculate the junction temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. For thermal resistance information see the Thermal Protection section. For this example, using the DRB package, the maximum junction temperature rise is calculated to be 45°C. The maximum junction temperature rise is calculated by adding junction temperature rise to the maximum ambient temperature. In this example, the maximum junction temperature is 100°C. Keep in mind the maximum junction temperate must be below 125°C for reliable operation. Addition ground planes, added thermal vias, and air flow all help to lower the maximum junction temperature. Using the DCQ or DBV packages are not recommended for this application due to the excessive junction temperature rise that is incurred.

To get the noise level below 30µV_RMS, a noise reduction capacitance (C_NR) of 10nF is selected along with an output capacitance of 10μF. Referencing the Output Noise section, the RMS noise can be calculated to be 28µV_RMS.

Use of an input capacitor is optional. However, in systems where the input supply is located several inches away from the LDO, a small 0.1µF input capacitor is recommended to negate the adverse effects that input supply inductance has on stability and ac performance.

In the same way as with designing with a fixed output voltage, the first step is to examine the maximum load current along with the input and output voltage requirements to determine if the device thermal and dropout voltage requirements are met. At 0.4A, the maximum dropout voltage is 200mV. Since the input voltage is 5V and the output voltage is 2.5V, there is more than sufficient voltage headroom to avoid dropout and maintain good PSRR.

The maximum power dissipated in the linear regulator is the maximum voltage dropped across the pass transistor from the input to the output times the maximum load current. In this example, the maximum voltage drop across in the pass transistor is 5V + 3% (5.15 V) minus 2.5V – 1% (2.475V) or 2.675V. The power dissipated in the pass transistor is calculated by taking this voltage drop multiplied by the maximum load current. For this example, the maximum power dissipated in the linear regulator is 1.07W. Once the power dissipated in the linear regulator is known, the corresponding junction temperature rise can be calculated. To calculate the junction temperature rise above ambient, the power dissipated must be multiplied by the junction-to-ambient thermal resistance. For thermal resistance information, see the Thermal Information table. For this example, using the DRB package, the maximum junction temperature rise is calculated to be 51°C. The maximum junction temperature rise is calculated by adding junction temperature rise to the maximum ambient temperature. In this example, the maximum junction temperature is 106°C. Keep in mind the maximum junction temperate must be below 125°C for reliable operation. Addition ground planes, added thermal vias, and air flow all help to lower the maximum junction temperature. Using the DCQ or DBV packages are not recommended for this application due to the excessive junction temperature rise that is incurred.

R₁ and R₂ can be calculated for any output voltage using the formula shown in Figure 7-2. Sample resistor values for common output voltages are shown in Figure 6-2.

For best accuracy, make the parallel combination of R₁ and R₂ approximately equal to 19kΩ. This 19kΩ, in addition to the internal 8kΩ resistor, presents the same impedance to the error amplifier as the 27kΩ bandgap reference output. This impedance helps compensate for leakages into the error amplifier terminals.

Using the values in Figure 6-2 for a 2.5V output results in a value of 39.2kΩ for R₁ and 36.5kΩ for R₂.

To get the noise level below 35µV_RMS, a noise reduction capacitance (C_FF) of 10nF is selected. Figure 5-47 must be used as a reference when selecting optimal value for C_FF.

A 10µF, low equivalent series resistance (ESR) ceramic X5R capacitor was used on the output of this design to minimize the output voltage droop during a low transient. Use of an input capacitor is optional. However, in systems where the input supply is located several inches away from the LDO, a small 0.1µF input capacitor is recommended to negate the adverse effects that input supply inductance has on stability and ac performance. See the Input and Output Capacitor Requirements section for additional information about input and output capacitor selection.