SBVS065L December   2005  – December 2024 TPS74301

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configurations and Functions
    1.     Pin Descriptions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Enable/Shutdown
      2. 6.3.2 Power-Good (QFN Package Only)
      3. 6.3.3 Internal Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input, Output, and Bias Capacitor Requirements
      2. 7.1.2 Transient Response
      3. 7.1.3 Dropout Voltage
      4. 7.1.4 Programmable Sequencing With Track
      5. 7.1.5 Sequencing Requirements
    2. 7.2 Typical Application
      1. 7.2.1 Adjustable Voltage Part and Setting
        1.       34
      2. 7.2.2 Design Requirements
      3. 7.2.3 Detailed Design Procedure
      4. 7.2.4 Application Performance Plots
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Layout Recommendations and Power Dissipation
      2. 7.4.2 Layout Example
      3. 7.4.3 Thermal Protection
      4. 7.4.4 Estimating Junction Temperature
  9. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
      2. 8.1.2 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Pin Descriptions

Table 4-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NAME KTW (DDPAK) RGW (QFN)
Bias 6 10 I Bias input voltage for error amplifier, reference, and internal control circuits.
EN 7 11 I Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left floating.
FB 2 16 I This pin is the feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
GND 4 12 G Ground.
IN 5 5–8 I Unregulated input to the device.
NC N/A 2–4, 13, 14, 17 — No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
OUT 3 1, 18–20 O Regulated output voltage. No capacitor is required on this pin for stability.
PAD/TAB — — — Must be soldered to the ground plane for increased thermal performance.
PG — 9 O Power-Good (PG) is an open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pullup resistor from 10kΩ to 1MΩ must be connected from this pin to a supply up to 5.5V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left floating if output monitoring is not necessary.
TRACK 1 15 I Tracking pin. Connect this pin to the center tap of a resistor divider off of an external supply to program the device to track an external supply.
(1) I = Input, O = Output, I/O = Input or Output, G = Ground, P = Power, N/A = Not applicable.