SBVS311A November 2019 – March 2020 TPS7A54
For proper operation of the power-good circuit, the pullup resistor value must be between 10 kΩ and 100 kΩ. The lower limit of 10 kΩ results from the maximum pulldown strength of the power-good transistor, and the upper limit of 100 kΩ results from the maximum leakage current at the power-good node. If the pullup resistor is outside of this range, then the power-good signal may not read a valid digital logic level.
Using a large CFF with a small CNR/SS causes the power-good signal to incorrectly indicate that the output voltage has settled during turnon. The CFF time constant must be greater than the soft-start time constant for proper operation of the PG during start-up. For a detailed description, see the Pros and Cons of Using a Feed-Forward Capacitor with a Low Dropout Regulator application report.
The state of PG is only valid when the device operates above the minimum supply voltage. During short UVLO events and at light loads, power-good does not assert because the output voltage is sustained by the output capacitance.