SBVS311A November 2019 – March 2020 TPS7A54
The UVLO circuit makes sure that the device remains disabled before the input or bias supplies reach the minimum operational voltage range, and that the device shuts down when the input supply or bias supply falls too low.
The UVLO circuit has a minimum response time of several microseconds to fully assert. During this time, a downward line transient below approximately 0.8 V causes the UVLO to assert for a short time; however, the UVLO circuit does not have enough stored energy to fully discharge the internal circuits inside of the device. When the UVLO circuit does not fully discharge, the internal circuits of the output are not fully disabled.
The effect of the downward line transient can be mitigated by either using a larger input capacitor to limit the fall time of the input supply when operating near the minimum VIN, or by using a bias rail.
Figure 45 shows the UVLO circuit response to various input voltage events. The diagram can be separated into the following regions: