SBVS397A September   2023  – November 2023 TPS7B4256-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Tracker Output Voltage (VOUT)
        1. 6.3.1.1 Output Voltage Equal to Reference Voltage
        2. 6.3.1.2 Output Voltage Less Than the Reference Voltage
        3. 6.3.1.3 Output Voltage Larger Than the Reference Voltage
      2. 6.3.2 Reverse Current Protection
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Thermal Protection
      5. 6.3.5 Current Limit
      6. 6.3.6 Output Short to Battery
      7. 6.3.7 Tracking Regulator With an Enable Circuit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Normal Operation
      2. 6.4.2 Dropout Operation
      3. 6.4.3 Operation With VIN < 3 V
      4. 6.4.4 Disable With ADJ/EN Control
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Dropout Voltage
      2. 7.1.2 Reverse Current
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input and Output Capacitor Selection
        2. 7.2.2.2 Feedback Resistor Selection
        3. 7.2.2.3 Feedforward Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package Mounting
        2. 7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
        3. 7.4.1.3 Power Dissipation and Thermal Considerations
        4. 7.4.1.4 Thermal Performance Versus Copper Area
        5. 7.4.1.5 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.3 Application Curves

The following images illustrate the functions of RθJA and ψJB versus copper area and thickness for the SOIC-8 (D) and HSOIC-8 (DDA) packages. These plots are generated with a 101.6-mm × 101.6-mm × 1.6-mm PCB of two and four layers. For the 2-layer board, the bottom layer is a ground plane of constant size, and the top layer copper is connected to GND and varied. For the 4-layer board, the second layer is a ground plane of constant size, the third layer is a power plane of constant size, and the top and bottom layers copper fills are connected to GND and varied at the same rate. For the 4-layer board, inner planes use 1-oz copper thickness. Outer layers are simulated with both 1-oz and 2-oz copper thickness. A 3 × 3 array of thermal vias with a 300-µm drill diameter and 25-µm copper plating is located underneath the device. The thermal vias connect the top layer, the bottom layer and, in the case of the 4-layer board, the first inner GND plane. PowerPAD™ Thermally Enhanced Package application note discusses the impact that thermal vias have on thermal performance.

GUID-20231026-SS0I-Z2K3-RXZD-5NTT6P9WX4DJ-low.svgFigure 7-4 RθJA vs Copper Area (SOIC-8 Package)
GUID-20231026-SS0I-LTJ9-FQBZ-8BN4XFBCRXLH-low.svgFigure 7-6 RθJA vs Copper Area (HSOIC-8 Package)
GUID-20231026-SS0I-C4RB-MDXN-PHKHMS7M7MLD-low.svgFigure 7-5 ψJB vs Copper Area (SOIC-8 Package)
GUID-20231026-SS0I-D2JM-W6GQ-PLKG3BD30J9H-low.svgFigure 7-7 ψJB vs Copper Area (HSOIC-8 Package)