SBVS363B December   2020  – November 2025 TPS7B87-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagrams
    3. 6.3 Feature Description
      1. 6.3.1 Power-Good (PG)
      2. 6.3.2 Adjustable Power-Good Delay Timer (DELAY)
      3. 6.3.3 Undervoltage Lockout
      4. 6.3.4 Thermal Shutdown
      5. 6.3.5 Current Limit
    4. 6.4 Device Functional Modes
      1. 6.4.1 Device Functional Mode Comparison
      2. 6.4.2 Normal Operation
      3. 6.4.3 Dropout Operation
      4. 6.4.4 Disabled
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Input and Output Capacitor Selection
      2. 7.1.2 Dropout Voltage
      3. 7.1.3 Reverse Current
      4. 7.1.4 Power Dissipation (PD)
        1. 7.1.4.1 Thermal Performance Versus Copper Area
        2. 7.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 7.1.5 Estimating Junction Temperature
      6. 7.1.6 Pulling Up the PG Pin to a Different Voltage
      7. 7.1.7 Power-Good
        1. 7.1.7.1 Setting the Adjustable Power-Good Delay
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Input Capacitor
        2. 7.2.2.2 Output Capacitor
      3. 7.2.3 Application Curves
    3. 7.3 Power Supply Recommendations
    4. 7.4 Layout
      1. 7.4.1 Layout Guidelines
        1. 7.4.1.1 Package Mounting
        2. 7.4.1.2 Board Layout Recommendations to Improve PSRR and Noise Performance
      2. 7.4.2 Layout Examples
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DDA|8
  • KVU|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.4 Thermal Information

THERMAL METRIC(1)(2) TPS7B87-Q1 UNIT
KVU DDA
5 PINS 8 PINS (ASO : ASE) (3) 8 PINS (ASO : FMX) (3)
RθJA Junction-to-ambient thermal resistance 29.7 41.8    42.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 40.2 55    57.5 °C/W
RθJB Junction-to-board thermal resistance 8.6 17.3    17.8 °C/W
ψJT Junction-to-top characterization parameter 2.9 4.5     5.6 °C/W
ψJB Junction-to-board characterization parameter 8.5 17.3     17.9 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.5 5.7    7.5 °C/W
(1) The thermal data is based on the JEDEC standard high K profile, JESD 51-7. Two-signal, two-plane, four-layer board with 2oz. copper. The copper pad is soldered to the thermal land pattern. Also, correct attachment procedure must be incorporated.
(2) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.
(3) See nomenclature table for more information regarding ASO