SLVSBC6C March   2013  – December 2019 TPS84A20

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Application
  4. 4 Revision History
  5. 5 Ordering Information
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Package Specifications
    4. 6.4 Electrical Characteristics
    5. 6.5 Thermal Information
  7. 7 Device Information
    1. 7.1      Functional Block Diagram
    2. Table 1. Pin Descriptions
  8. 8 Typical Characteristics (PVIN = VIN = 12 V)
  9. 9 Typical Characteristics (PVIN = VIN = 5 V)
  10. 10Typical Characteristics (PVIN = 3.3 V, VIN = 5 V)
  11. 11Application Information
    1. 11.1  Adjusting the Output Voltage
    2. 11.2  Capacitor Recommendations for the TPS84A20 Power Supply
      1. 11.2.1 Capacitor Technologies
        1. 11.2.1.1 Electrolytic, Polymer-Electrolytic Capacitors
        2. 11.2.1.2 Ceramic Capacitors
        3. 11.2.1.3 Tantalum, Polymer-Tantalum Capacitors
      2. 11.2.2 Input Capacitor
      3. 11.2.3 Output Capacitor
    3. 11.3  Transient Response
    4. 11.4  Transient Waveforms
    5. 11.5  Application Schematics
    6. 11.6  VIN and PVIN Input Voltage
    7. 11.7  3.3 V PVIN Operation
    8. 11.8  Power Good (PWRGD)
    9. 11.9  Light Load Efficiency (LLE)
    10. 11.10 SYNC_OUT
    11. 11.11 Parallel Operation
    12. 11.12 Power-Up Characteristics
    13. 11.13 Pre-Biased Start-Up
    14. 11.14 Remote Sense
    15. 11.15 Thermal Shutdown
    16. 11.16 Output On/Off Inhibit (INH)
    17. 11.17 Slow Start (SS/TR)
    18. 11.18 Overcurrent Protection
    19. 11.19 Synchronization (CLK)
    20. 11.20 Sequencing (SS/TR)
    21. 11.21 Programmable Undervoltage Lockout (UVLO)
    22. 11.22 Layout Considerations
    23. 11.23 EMI
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Support Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RVQ|42
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Device Information

7.1 Functional Block Diagram

TPS84A20 TPS84A20 Internal Block OCP.gif

Table 1. Pin Descriptions

TERMINAL DESCRIPTION
NAME NO.
AGND 2 Zero volt reference for the analog control circuit. These pins are not connected together internal to the device and must be connected to one another using an AGND plane of the PCB. These pins are associated with the internal analog ground (AGND) of the device. See Layout Considerations.
23
PGND 20 This is the return current path for the power stage of the device. Connect these pins to the load and to the bypass capacitors associated with PVIN and VOUT.
21
31
32
33
VIN 3 Input bias voltage pin. Supplies the control circuitry of the power converter. Connect this pin to the input bias supply. Connect bypass capacitors between this pin and PGND.
PVIN 1 Input switching voltage. Supplies voltage to the power switches of the converter. Connect these pins to the input supply. Connect bypass capacitors between these pins and PGND.
11
12
39
40
VOUT 34 Output voltage. These pins are connected to the internal output inductor. Connect these pins to the output load and connect external bypass capacitors between these pins and PGND.
35
36
37
38
41
PH 10 Phase switch node. These pins must be connected to one another using a small copper island under the device for thermal relief. Do not place any external component on these pins or tie them to a pin of another function.
13
14
15
16
17
18
19
42
DNC 5 Do not connect. Do not connect these pins to AGND, to another DNC pin, or to any other voltage. These pins are connected to internal circuitry. Each pin must be soldered to an isolated pad.
9
24
ISHARE 25 Current share pin. Connect this pin to other TPS84A20 devices ISHARE pin when paralleling multiple TPS84A20 devices. When unused, treat this pin as a Do Not Connect (DNC) and leave it isolated from all other signals or ground.
OCP_SEL 4 Over current protection select pin. Leave this pin open for hiccup mode operation. Connect this pin to AGND for cycle-by-cycle operation. See Overcurrent Protection for more details.
ILIM 6 Current limit pin. Leave this pin open for full current limit threshold. Connect this pin to AGND to reduce the current limit threshold by approximately 20%.
SYNC_OUT 7 Synchronization output pin. Provides a 180° out-of-phase clock signal.
PWRGD 8 Power Good flag pin. This open drain output asserts low if the output voltage is more than approximately ±6% out of regulation. A pullup resistor is required.
RT/CLK 22 This pin is connected to an internal frequency setting resistor which sets the default switching frequency. An external resistor can be connected from this pin to AGND to increase the frequency. This pin can also be used to synchronize to an external clock.
VADJ 26 Connecting a resistor between this pin and AGND sets the output voltage.
SENSE+ 27 Remote sense connection. This pin must be connected to VOUT at the load or at the device pins. Connect this pin to VOUT at the load for improved regulation.
SS/TR 28 Slow-start and tracking pin. Connecting an external capacitor to this pin adjusts the output voltage rise time. A voltage applied to this pin allows for tracking and sequencing control.
STSEL 29 Slow-start or track feature select. Connect this pin to AGND to enable the internal SS capacitor. Leave this pin open to enable the TR feature.
INH/UVLO 30 Inhibit and UVLO adjust pin. Use an open drain or open collector logic device to ground this pin to control the INH function. A resistor divider between this pin, AGND, and PVIN/VIN sets the UVLO voltage.
RVQ PACKAGE
(TOP VIEW)
TPS84A20 pinout_rvq_42_pinnames OCP.gif