11.19 Synchronization (CLK)

An internal phase locked loop (PLL) has been implemented to allow synchronization between 200 kHz and 1200 kHz, and to easily switch from RT mode to CLK mode. To implement the synchronization feature, connect a square wave clock signal to the RT/CLK pin with a duty cycle between 20% to 80%. The clock signal amplitude must transition lower than 0.5 V and higher than 2.0 V. The start of the switching cycle is synchronized to the falling edge of RT/CLK pin. In applications where both RT mode and CLK mode are needed, the device can be configured as shown in Figure 37.

Before the external clock is present, the device works in RT mode and the switching frequency is set by RT resistor. When the external clock is present, the CLK mode overrides the RT mode. The first time the CLK pin is pulled above the RT/CLK high threshold (2.0 V), the device switches from RT mode to CLK mode and the RT/CLK pin becomes high impedance as the PLL starts to lock onto the frequency of the external clock. It is not recommended to switch from CLK mode back to RT mode because the internal switching frequency drops to 100 kHz first before returning to the switching frequency set by the RT resistor (R_RT).

Figure 37. RT/CLK Configuration

The switching frequency must be selected based on the output voltages of the devices being synchronized. Table 8 shows the allowable frequencies for a given range of output voltages. The allowable switching frequency changes based on the maximum output current (I_OUT) of an application. The table shows the V_OUT range when I_OUT ≤ 10 A, 9 A, and 8 A. For the most efficient solution, always synchronize to the lowest allowable frequency. For example, an application requires synchronizing three TPS84A20 devices with output voltages of 1.0 V, 1.2 V and 1.8 V, all powered from PVIN = 12 V. Table 8 shows that all three output voltages should be synchronized to 300 kHz.