SNVSC83C September   2022  – October 2025 TPSM365R3 , TPSM365R6

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  System Characteristics
    7. 6.7  Typical Characteristics
    8. 6.8  Typical Characteristics: VIN = 12 V
    9. 6.9  Typical Characteristics: VIN = 24 V
    10. 6.10 Typical Characteristics: VIN = 48 V
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Input Voltage Range
      2. 7.3.2  Output Voltage Selection
      3. 7.3.3  Input Capacitors
      4. 7.3.4  Output Capacitors
      5. 7.3.5  Enable, Start-Up, and Shutdown
      6. 7.3.6  External CLK SYNC (with MODE/SYNC)
        1. 7.3.6.1 Pulse-Dependent MODE/SYNC Pin Control
      7. 7.3.7  Switching Frequency (RT)
      8. 7.3.8  Power-Good Output Operation
      9. 7.3.9  Internal LDO, VCC UVLO, and BIAS Input
      10. 7.3.10 Bootstrap Voltage and VBOOT-UVLO (BOOT Terminal)
      11. 7.3.11 Spread Spectrum
      12. 7.3.12 Soft Start and Recovery from Dropout
        1. 7.3.12.1 Recovery from Dropout
      13. 7.3.13 Overcurrent Protection (OCP)
      14. 7.3.14 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Shutdown Mode
      2. 7.4.2 Standby Mode
      3. 7.4.3 Active Mode
        1. 7.4.3.1 CCM Mode
        2. 7.4.3.2 AUTO Mode - Light Load Operation
          1. 7.4.3.2.1 Diode Emulation
          2. 7.4.3.2.2 Frequency Reduction
        3. 7.4.3.3 FPWM Mode - Light Load Operation
        4. 7.4.3.4 Minimum On-time (High Input Voltage) Operation
      4. 7.4.4 Dropout
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 600-mA and 300-mA Synchronous Buck Regulator for Industrial Applications
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Custom Design With WEBENCH® Tools
          2. 8.2.1.2.2  Output Voltage Setpoint
          3. 8.2.1.2.3  Switching Frequency Selection
          4. 8.2.1.2.4  Input Capacitor Selection
          5. 8.2.1.2.5  Output Capacitor Selection
          6. 8.2.1.2.6  VCC
          7. 8.2.1.2.7  CFF Selection
          8. 8.2.1.2.8  Power-Good Signal
          9. 8.2.1.2.9  Maximum Ambient Temperature
          10. 8.2.1.2.10 Other Connections
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Ground and Thermal Considerations
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Third-Party Products Disclaimer
      2. 9.1.2 Device Nomenclature
      3. 9.1.3 Development Support
        1. 9.1.3.1 Custom Design With WEBENCH® Tools
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.4 Thermal Information

THERMAL METRIC (1) TPSM365R6 / TPSM365R3 UNIT
RDN
11 Pins
RθJA Junction-to-ambient thermal resistance 56.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.9 °C/W
RθJB Junction-to-board thermal resistance 17.3 °C/W
ΨJT Junction-to-top characterization parameter 10.7 °C/W
ΨJB Junction-to-board characterization parameter 17.2 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.  The value of RΘJA given in this table is only valid for comparison with other packages and can not be used for design purposes. This value was calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. It does not represent the performance obtained in an actual application.