SLWS245B May   2014  – February 2017 TRF3722

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Typical Characteristics
      1. 6.6.1 Modulator Output Spectrum
    7. 6.7  Typical Characteristics - Output Power
    8. 6.8  Typical Characteristics - Gain
    9. 6.9  Typical Characteristics - OIP3
    10. 6.10 Typical Characteristics - OIP2
    11. 6.11 Typical Characteristics - OP1dB
    12. 6.12 Typical Characteristics - Noise
    13. 6.13 Typical Characteristics - Unadjusted CF
    14. 6.14 Typical Characteristics - Unadjusted SBS
    15. 6.15 Typical Characteristics - LO Harmonic
    16. 6.16 Typical Characteristics - BB Harmonic
    17. 6.17 Typical Characteristics - RF Output Return Loss
    18. 6.18 Typical Characteristics - PLL/VCO
    19. 6.19 Typical Characteristics - Current Consumption
    20. 6.20 Typical Characteristics - Power Dissipation
  7. 7 Parameter Measurement Information
    1. 7.1 Serial Interface Timing Diagram
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 RF Output
      2. 8.3.2 Baseband Inputs
      3. 8.3.3 LO Output
      4. 8.3.4 PLL Architecture
      5. 8.3.5 External VCO
      6. 8.3.6 Loop Filter
      7. 8.3.7 Lock Detect
    4. 8.4 Device Functional Modes
      1. 8.4.1 Selecting PLL Divider Values
      2. 8.4.2 Setup Example for Integer Mode
      3. 8.4.3 Integer and Fractional Mode Selection
      4. 8.4.4 Selecting the VCO and VCO Frequency Control
    5. 8.5 Register Maps
      1. 8.5.1 Serial interface Register Definition
        1. 8.5.1.1 BIAS SETTINGS
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedures: DAC to Modulator Interface Network
      3. 9.2.3 Application Curves: DAC34H84 with TRF3722 Modulator Performance
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

7.1 Serial Interface Timing Diagram

The TRF3722 features a four-wire serial programming interface (4WI) that controls an internal 32-bit shift register with seven parallel registers. There are total of three signals that must be applied: the clock (CLK), the serial data (DATA), and the latch enable (LE). The fouth signal is the read back (RDBK) signal. The serial data (DB0-DB31) are loaded least significant bit (LSB) first, and read on the rising edge of the CLK. LE is asynchronous to the CLK signal; at its rising edge, the data in the shift register are loaded into the selected internal register. Figure 130 shows the timing diagram the 4WI. Table 1 lists the 4WI timing for the write operation.

TRF3722 spi_time_diagram_slws245.gif Figure 130. 4WI Writing Timing Diagram

Table 1. 4WI Timing for Write Operation

MIN TYP MAX UNIT
th Hold time, data to clock 20 ns
tSU1 Setup time, data to clock 20 ns
tCH Clock low duration 20 ns
tCL Clock High duration 20 ns
tSU2 Setup time, clock to enable 20 ns
tCLK Clock period 50 ns
tW Enable Time 50 ns
tSU3 Setup time, Latch to Data 70 ns

TRF3722 integrates 7 registers: Register 0 (000) to Register 6 (110). Registers 1 through 6 are used to set-up and control the TRF3722 functionalities, while register 0 is used for the read-back function. Each read-back is composed by two phases: writing followed by the actual reading of the internal data. This is shown in the timing diagram in Figure 131.

TRF3722 spi_read_timing_slws245.gif Figure 131. 4WI Read-Back Timing Diagram

During the writing phase a command is sent to TRF3722 register 0 to set it in read-back mode and to specify which register is to be read. In the proper reading phase, at each rising clock edge, the internal data is transferred into the RDBK pin and can be read at the following falling edge (LSB first). The first clock after the LE goes high (end of writing cycle) is idle and the following 32 clocks pulses will transfer the internal register content to the RDBK pin. Table 2 shows the Readback timing.

Table 2. 4WI Timing for Readback Timing

MIN TYP MAX UNIT COMMENT
th Hold time, data to clock 20 ns
tSU1 Setup time, data to clock 20 ns
tCH Clock low duration 20 ns
tCL Clock High duration 20 ns
tSU2 Setup time, clock to enable 20 ns
tSU3 Setup time, enable to Readback clock 20 ns
td Delay time, clock to Readback data output 10
tW Enable Time 50 ns Equals Clock period
t(CLK) Clock period 50 ns