SLLSEE5D february   2013  – july 2023 TUSB8040A1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-9FC00080-214A-41B8-A47D-B9F7BA87DE22/SLLSE42922
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 3.3-V I/O Electrical Characteristics
    6. 6.6 Hub Input Supply Current
    7. 6.7 Timing and Switching Characteristics
      1. 6.7.1 Clock Generation
      2. 6.7.2 Crystal Requirements
      3. 6.7.3 Input Clock Requirements
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
    4. 7.4 I2C EEPROM Operation
    5. 7.5 SMBus Target Operation
    6. 7.6 Configuration Registers
      1. 7.6.1  ROM Signature Register
      2. 7.6.2  Vendor ID LSB Register
      3. 7.6.3  Vendor ID MSB Register
      4. 7.6.4  Product ID LSB Register
      5. 7.6.5  Product ID MSB Register
      6. 7.6.6  Device Configuration Register
      7. 7.6.7  Battery Charging Support Register
      8. 7.6.8  Device Removable Configuration Register
      9. 7.6.9  Port Used Configuration Register
      10. 7.6.10 Reserved Register
      11. 7.6.11 Reserved Register
      12. 7.6.12 Language ID LSB Register
      13. 7.6.13 Language ID MSB Register
      14. 7.6.14 Serial Number String Length Register
      15. 7.6.15 Manufacturer String Length Register
      16. 7.6.16 Product String Length Register
      17. 7.6.17 Reserved Register
      18. 7.6.18 Serial Number Registers
      19. 7.6.19 Manufacturer String Registers
      20. 7.6.20 Product String Registers
      21. 7.6.21 Additional Feature Configuration Register
      22. 7.6.22 Reserved Register
      23. 7.6.23 Reserved Register
      24. 7.6.24 Device Status and Command Register
  9. 8Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Upstream Port Implementation
        2. 8.2.2.2 Downstream Port 1 Implementation
        3. 8.2.2.3 Downstream Port 2 Implementation
        4. 8.2.2.4 Downstream Port 3 Implementation
        5. 8.2.2.5 Downstream Port 4 Implementation
        6. 8.2.2.6 VBUS Power Switch Implementation
        7. 8.2.2.7 Clock, Reset, I2C/SMBUS, and Misc
        8. 8.2.2.8 Power Implementation
      3. 8.2.3 Application Curve
      4. 8.2.4 Power Supply Recommendations
        1. 8.2.4.1 Power Up and Reset
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
          1. 8.2.5.1.1 Part Placement
          2. 8.2.5.1.2 Board Layout Considerations
            1. 8.2.5.1.2.1  RKM Package – QFN (Quad Flat No-Lead)
            2. 8.2.5.1.2.2  Impedance
            3. 8.2.5.1.2.3  Critical Signals
            4. 8.2.5.1.2.4  Crystal
            5. 8.2.5.1.2.5  USB Interface
            6. 8.2.5.1.2.6  Differential Pair Signals
              1. 8.2.5.1.2.6.1 Internal Bond Wire Mismatch
            7. 8.2.5.1.2.7  Port Connectors
            8. 8.2.5.1.2.8  Reset Terminals
            9. 8.2.5.1.2.9  Miscellaneous Terminals
            10. 8.2.5.1.2.10 Power Control and Battery Charging Terminals
            11. 8.2.5.1.2.11 USB 2.0 Port Indicator LED Terminals
          3. 8.2.5.1.3 Power
            1. 8.2.5.1.3.1 Power
            2. 8.2.5.1.3.2 Downstream Port Power
            3. 8.2.5.1.3.3 Ground
        2. 8.2.5.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.6.6 Device Configuration Register

Figure 7-6 Register Offset 5h
76543210
customStringscustomSernumu1u2DisableportIndzgangedfullPwrMgmtzu1u2TimerOvrRSVD
RW-0RW-XRO-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 7-7 Bit Descriptions – Device Configuration Register
BITFIELD NAMEACCESSDESCRIPTION
7customStringsRWCustom Strings Enable. When this bit is set and the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads the string registers from the contents of the EEPROM. When set and the TUSB8040A1 is in SMBUS mode, the string registers may written by an SMBus host. This bit defaults to 0.
6customSernumRWCustom Serial Number Enable. When this bit is set and the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads the serial number register from the contents of the EEPROM. When set and the TUSB8040A1 is in SMBUS mode, the Serial Number registers may written by an SMBus host. This bit defaults to 0.
5u1u2DisableRWU1 U2 Disable. When this bit is set the TUSB8040A1 will not initiate or accept any U1 or U2 requests on any port, upstream or downstream, unless it receives or sends a Force_LinkPM_Accept LMP. After receiving or sending an FLPMA LMP, it will continue to enable U1 and U2 according to USB 3.0 protocol until it gets a power-on reset or is disconnected on its upstream port. This bit is loaded at the de-assertion of reset with the value of the SDA_SMBDAT terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be over-written by an SMBus host.
4portIndzRWPort Indicator Status. This bit shall be loaded at the de-assertion of reset with the value of PORTINDz_SMBA3 terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be overwritten by an SMBus host.
3gangedRWGanged. This bit shall be loaded at the de-assertion of reset with the value of GANGEd_SMBA2 terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be overwritten by an SMBus host.
2fullPwrMgmtzRWFull Power Management. This bit is loaded at the de-assertion of reset with the value of the FULLPWRMGMTz_SMBA1 terminal. When this bit is 0, power switching and over-current detection is supported whether bus- or self-powered. When the bit is 1 and the device is bus powered, power switching is supported but over-current detection is not supported. When the bit is 1 and the device is self-powered over-current detection is supported but power switching is not supported. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be over-written by an SMBus host.
1u1u2TimerOvrRWU1 U2 Timer Override. When this bit is set the TUSB8040A1 will override the downstream ports u1/u2 timeout values set by software. If software sets a value in the range of 1-FF, the TUSB8040A1 will use the value FF. If software sets a value of 0, the TUSB8040A1 will use the value 0.This bit is loaded at the de-assertion of reset with the value of the SCL_SMBCLK terminal. When the TUSB8040A1 is in I2C mode, the TUSB8040A1 loads this bit from the contents of the EEPROM. When the TUSB8040A1 is in SMBUS mode, the value may be over-written by an SMBus host.
0RSVDROReserved. Read only, returns 0 when read.