SLLSEE5D february   2013  – july 2023 TUSB8040A1

PRODUCTION DATA  

  1.   1
  2. 1Features
  3. 2Applications
  4. 3Description
  5. 4Revision History
  6. 5Pin Configuration and Functions
  7. 6Specifications
    1. 6.1 Absolute Maximum Ratings #GUID-9FC00080-214A-41B8-A47D-B9F7BA87DE22/SLLSE42922
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 3.3-V I/O Electrical Characteristics
    6. 6.6 Hub Input Supply Current
    7. 6.7 Timing and Switching Characteristics
      1. 6.7.1 Clock Generation
      2. 6.7.2 Crystal Requirements
      3. 6.7.3 Input Clock Requirements
  8. 7Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Memory
    4. 7.4 I2C EEPROM Operation
    5. 7.5 SMBus Target Operation
    6. 7.6 Configuration Registers
      1. 7.6.1  ROM Signature Register
      2. 7.6.2  Vendor ID LSB Register
      3. 7.6.3  Vendor ID MSB Register
      4. 7.6.4  Product ID LSB Register
      5. 7.6.5  Product ID MSB Register
      6. 7.6.6  Device Configuration Register
      7. 7.6.7  Battery Charging Support Register
      8. 7.6.8  Device Removable Configuration Register
      9. 7.6.9  Port Used Configuration Register
      10. 7.6.10 Reserved Register
      11. 7.6.11 Reserved Register
      12. 7.6.12 Language ID LSB Register
      13. 7.6.13 Language ID MSB Register
      14. 7.6.14 Serial Number String Length Register
      15. 7.6.15 Manufacturer String Length Register
      16. 7.6.16 Product String Length Register
      17. 7.6.17 Reserved Register
      18. 7.6.18 Serial Number Registers
      19. 7.6.19 Manufacturer String Registers
      20. 7.6.20 Product String Registers
      21. 7.6.21 Additional Feature Configuration Register
      22. 7.6.22 Reserved Register
      23. 7.6.23 Reserved Register
      24. 7.6.24 Device Status and Command Register
  9. 8Applications, Implementation, and Layout
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Upstream Port Implementation
        2. 8.2.2.2 Downstream Port 1 Implementation
        3. 8.2.2.3 Downstream Port 2 Implementation
        4. 8.2.2.4 Downstream Port 3 Implementation
        5. 8.2.2.5 Downstream Port 4 Implementation
        6. 8.2.2.6 VBUS Power Switch Implementation
        7. 8.2.2.7 Clock, Reset, I2C/SMBUS, and Misc
        8. 8.2.2.8 Power Implementation
      3. 8.2.3 Application Curve
      4. 8.2.4 Power Supply Recommendations
        1. 8.2.4.1 Power Up and Reset
      5. 8.2.5 Layout
        1. 8.2.5.1 Layout Guidelines
          1. 8.2.5.1.1 Part Placement
          2. 8.2.5.1.2 Board Layout Considerations
            1. 8.2.5.1.2.1  RKM Package – QFN (Quad Flat No-Lead)
            2. 8.2.5.1.2.2  Impedance
            3. 8.2.5.1.2.3  Critical Signals
            4. 8.2.5.1.2.4  Crystal
            5. 8.2.5.1.2.5  USB Interface
            6. 8.2.5.1.2.6  Differential Pair Signals
              1. 8.2.5.1.2.6.1 Internal Bond Wire Mismatch
            7. 8.2.5.1.2.7  Port Connectors
            8. 8.2.5.1.2.8  Reset Terminals
            9. 8.2.5.1.2.9  Miscellaneous Terminals
            10. 8.2.5.1.2.10 Power Control and Battery Charging Terminals
            11. 8.2.5.1.2.11 USB 2.0 Port Indicator LED Terminals
          3. 8.2.5.1.3 Power
            1. 8.2.5.1.3.1 Power
            2. 8.2.5.1.3.2 Downstream Port Power
            3. 8.2.5.1.3.3 Ground
        2. 8.2.5.2 Layout Example
  10. 9Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11.   Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
8.2.5.1.2.9 Miscellaneous Terminals

The USB_R1 and USBR1_RTN terminals require a precision resistor. A 9.09-kΩ ±1% resistor should be placed in parallel across these terminals, as close to the device as possible.

While the TUSB8040A1 EVM can utilize external pull up and pull down resistors on these terminals, there are inherent pull-ups and pull-downs implemented within the TUSB8040A1.

Note:

The internal pull-up and pull-down resistors of the TUSB8040A1 have a nominal value of 22 kΩ (150 μA at 3.3 V). If using an external pull up on a terminal that has an internal pull- down resistor, TI recommends using a value of 7.5 kΩ or smaller. If using an external pull down on a terminal that has an internal pull-up resistor, TI recommends using a value of 7.5 kΩ or smaller.

  • SMBUSz – The I2C interface mode is enabled by default via the internal pull-up resistor on this terminal. If a 4.7-kΩ pull-down is placed on this terminal and sampled at power-on reset, SMBUS mode is enabled.
  • SDA_SMBDAT and SCL_SMBCLK – Serial EEPROM or SMBUS interface. On the EVM, these pins are routed to a serial EEPROM socket with 1-kΩ pull-up resistors installed on both signals. If the TUSB8040A1 is being used in SMBUS mode, then these signals become the data and clock signal, respectively. The TUSB8040A1 has internal pull-downs on these terminals.
    The SDA_SMBDAT terminal is sampled at the de-assertion of reset to determine if SS low power states U1 and U2 are disabled. If SDA_SMBDAT is high, U1 and U2 low power states are disabled. If SDA_SMBDAT is low, U1 and U2 low power states are enabled. Disabling U1 and U2 allows the TUSB8040A1 to work with USB 3.0 devices that do not implement low power states per the USB 3.0 specification. If the EEPROM or SMBUS is implemented, the value of the u1u2Disable bit in the Device Configuration Register determines if the low power states U1 and U2 are disabled.
    The SCL_SMBCLK terminal is sampled at the de-assertion of reset to determine if SuperSpeed low power state (U1 and U2) initiation is disabled. If SCL_SMBCLK is high, U1 and U2 low power state initiation is disabled. If SCL_SMBCLK is low, U1 and U2 low power states are completely enabled. Disabling U1 and U2 initiation allows the TUSB8040A1RKM to accept requests to enter low power states from the host or downstream devices, but it will not initiate the transitions. If the EEPROM or SMBUS is implemented, the value of the u1u2TimerOvr bit in the Device Configuration Register determines if the low power state initiation is disabled.
  • HS_SUSPEND_POLARITY – Downstream port power switch enable polarity is set to active high if a pull-up is placed on this terminal and sampled at power-on reset. The TUSB8040A1 has an internal pull-down on this terminal to set the power enables to active low by default. Since this terminal also acts as an LED output, a pull-up value of 330 Ω is recommended if an LED with series resistance of 1 kΩ is used for the status LED circuit.
  • SS_SUSPEND_SSC – Spread spectrum clocking is disabled if a pull-up is placed on this terminal and sampled at power-on reset. The TUSB8040A1 has an internal pull down on this terminal to enable SSC by default. Since this terminal also acts as an LED output, a pull-up value of 330 ohm is recommended if a LED with series resistance of 1K is used for the status LED circuit.