SLUS223H April   1997  – October 2024 UC1842 , UC1843 , UC1844 , UC1845 , UC2842 , UC2843 , UC2844 , UC2845 , UC3842 , UC3843 , UC3844 , UC3845

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1  Detailed Pin Description
        1. 7.3.1.1 COMP
        2. 7.3.1.2 VFB
        3. 7.3.1.3 ISENSE
        4. 7.3.1.4 RT/CT
        5. 7.3.1.5 GROUND
        6. 7.3.1.6 OUTPUT
        7. 7.3.1.7 VCC
        8. 7.3.1.8 VREF
      2. 7.3.2  Pulse-by-Pulse Current Limiting
      3. 7.3.3  Current-Sense
      4. 7.3.4  Error Amplifier With Low Output Resistance
      5. 7.3.5  Undervoltage Lockout
      6. 7.3.6  Oscillator
      7. 7.3.7  Synchronization
      8. 7.3.8  Shutdown Technique
      9. 7.3.9  Slope Compensation
      10. 7.3.10 Soft Start
      11. 7.3.11 Voltage Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 UVLO Mode
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Open-Loop Test Fixture
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1  Input Bulk Capacitor and Minimum Bulk Voltage
        2. 8.2.2.2  Transformer Turns Ratio and Maximum Duty Cycle
        3. 8.2.2.3  Transformer Inductance and Peak Currents
        4. 8.2.2.4  Output Capacitor
        5. 8.2.2.5  Current Sensing Network
        6. 8.2.2.6  Gate Drive Resistor
        7. 8.2.2.7  VREF Capacitor
        8. 8.2.2.8  RT/CT
        9. 8.2.2.9  Start-Up Circuit
        10. 8.2.2.10 Voltage Feedback Compensation
          1. 8.2.2.10.1 Power Stage Poles and Zeroes
          2. 8.2.2.10.2 Slope Compensation
          3. 8.2.2.10.3 Open-Loop Gain
          4. 8.2.2.10.4 Compensation Loop
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
        1. 8.4.1.1 Feedback Traces
        2. 8.4.1.2 Bypass Capacitors
        3. 8.4.1.3 Compensation Components
        4. 8.4.1.4 Traces and Ground Planes
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted) –55°C ≤ TA ≤ 125°C for the UC184x; –40°C ≤ TA ≤ 85°C for the UC284x, 0°C ≤ TA ≤ 70°C for the UC384x, VVCC = 15 V(2); 0.1 µF capacitor from VCC to GROUND, 0.1 µF capacitor from VREF to GROUND, RRT = 10 kΩ; CCT = 3.3 nF, TJ = TA.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
REFERENCE SECTION
VVREFReference voltageIVREF = 1 mA, TJ = 25°CUC184x and UC284x4.9555.05V
UC384x4.955.1
Line regulation12 ≤ VCC ≤ 25 V620mV
Load regulation1 ≤ IVREF ≤ 20 mA625mV
Temperature stabilitySee (1) (3)0.20.4mV/°C
Total output variationLine, load, temperature (1)UC184x and UC284x4.95.1V
UC384x4.825.18
Output noise voltage10 Hz ≤ fOSC ≤ 10 kHz, (1) TJ = 25°C50μV
Long term stabilityTA = 125°C, 1000 Hrs (1)525mV
Output short circuit–30–100–180mA
OSCILLATOR SECTION
fOSCInitial accuracyTJ = 25°C(5)475257kHz
Voltage stability12 ≤ VCC ≤ 25 V0.2%1%
Temperature stabilityTMIN ≤ TA ≤ TMAX (1)5%
VRT/CTAmplitudePeak-to-peak (1)1.7V
ERROR AMPLIFIER SECTION
VVFBInput voltageVCOMP = 2.5 VUC184x and UC284x2.452.52.55V
UC384x2.422.52.58
IVFBInput bias currentUC184x and UC284x–1µA
UC384x–2
AVOL2 ≤ VCOMP ≤ 4 V6590dB
Unity gain bandwidthTJ = 25°C (1)0.71MHz
PSRRPower supply rejection ratio12 ≤ VCC ≤ 25 V6070dB
I(snk)COMP sink currentVVFB = 2.7 V, VCOMP = 1.1 V26mA
I(src)COMP source currentVVFB = 2.3 V, VCOMP = 5 V–0.5–0.8
VCOMP HighHigh-level output voltageVVFB = 2.3 V, RL = 15-kΩ COMP to GROUND56V
VCOMP LowLow-level output voltageVVFB = 2.7 V, RL = 15-kΩ COMP to VREF0.71.1
CURRENT SENSE SECTION
ACSGainSee (4) (6)2.8533.15V/V
VISENSEMaximum input signalVCOMP = 5 V (4)0.911.1V
PSRRPower supply rejection ratio12 V ≤ VVCC ≤ 25 V (1) (4)70dB
IISENSEInput bias current–2–10µA
tDLYDelay to outputVISENSE stepped from 0 V to 2 V (1)150300ns
OUTPUT SECTION
VOUT LowLow-level OUTPUT voltageISINK = 20 mA0.10.4V
ISINK = 200 mA1.52.2
VOUT HighHigh-level OUTPUT voltageISOURCE = 20 mA1313.5V
ISOURCE = 200 mA1213.5
tRISERise time (1)COUTPUT = 1 nF, TJ = 25°C25150ns
tFALLFall time (1)COUTPUT = 1 nF, TJ = 25°C,25150ns
UNDERVOLTAGE LOCKOUT (UVLO)
VCCONEnable thresholdUC1842/4 and UC2842/4151617V
UC3842/414.51617.5
UCx843/57.88.49
VCCOFFUVLO off thresholdUC1842/4 and UC2842/491011V
UC3842/48.51011.5
UCx843/577.68.2
PWM
DMAXMaximum duty cycleUCx842/392%97%100%
UC1844/5 and UC2844/546%48%50%
UC3844/547%48%50%
DMINMinimum duty cycle0%
TOTAL STANDBY CURRENT
IVCCStart-up current0.51mA
IVCCOperating supply currentVVFB = VISENSE= 0 V1117
VCC Zener voltageIVCC = 25 mA3039V
(1) Specified by design. Not production tested.
(2) Adjust VCC above the start threshold before setting at 15 V
(3) Temperature stability, sometimes referred to as average temperature coefficient, is described by the equation:
UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845 UC2845 UC3845 VREFmin and VREFmax are the maximum and minimum reference voltages measured over the appropriate temperature range. Note that the extremes in voltage do not necessarily occur at the extremes in temperature.
(4) Parameter measured at trip point of latch with VFB = 0 V.
(5) OUTPUT switching frequency, fSW, equals the oscillator frequency, fOSC, for the UCx842 and UCx843. OUTPUT switching frequency, fSW, is one half oscillator frequency, fOSC, for the UCx844 and UCx845.
(6) Gain defined as: A = ΔVCOMP/ΔVISENSE, 0 V ≤ VISENSE ≤ 0.8 V.