SLUSAO7 Data sheet

SLUSAO7C September 2011 – July 2024 UCC28063

PRODUCTION DATA

Package Options

Mechanical Data (Package|Pins)

D|16
- MPDS178G

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.5 Electrical Characteristics

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, R_TSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40 °C < T_J = T_A < 125 °C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCC BIAS SUPPLY
VCC_SHUNT	VCC shunt voltage⁽¹⁾	I_VCC = 10 mA	22	24	26	V
I_VCC(ULVO)	VCC current, UVLO	VCC = 11.4 V prior to turn-on		95	200	µA
I_VCC(stby)	VCC current, disabled	VSENSE = 0 V		100	200	µA
I_VCC(on)	VCC current, enabled	VSENSE = 2 V		5	8	mA
UNDERVOLTAGE LOCKOUT (UVLO)
VCC_ON	VCC turn-on threshold	VCC rising	11.5	12.6	13.5	V
VCC_OFF	VCC turn-off threshold	VCC falling	9.5	10.35	11.5
	UVLO Hysteresis		1.85	2.15	2.45
REFERENCE
V_REF	VREF output voltage, no load	I_VREF = 0 mA	5.82	6.00	6.18	V
	VREF change with load	0 mA ≤ I_VREF ≤ −2 mA		−1	−6	mV
	VREF change with VCC	12 V ≤ VCC ≤ 20 V		2	10	mV
ERROR AMPLIFIER
VSENSEreg25	VSENSE input regulation voltage	T_A = 25 °C	5.85	6	6.15	V
VSENSEreg	VSENSE input regulation voltage		5.82	6	6.18	V
I_VSENSE	VSENSE input bias current	In regulation	50	100	150	nA
V_ENAB	VSENSE enable threshold, rising		1.15	1.25	1.35	V
	VSENSE enable hysteresis		0.02	0.07	0.15
V_COMPCLMP	COMP high voltage, clamped	VSENSE = VSENSEreg – 0.3 V	4.70	4.95	5.10
	COMP low voltage, saturated	VSENSE = VSENSEreg + 0.3 V		0.03	0.125
g_M	VSENSE to COMP transconductance, small signal	0.99(VSENSEreg) < VSENSE < 1.01(VSENSEreg), COMP = 3 V	40	55	70	µS
	VSENSE high-going threshold to enable COMP large signal gain, percent	Relative to VSENSEreg, COMP = 3 V	3.25%	5%	6.75%
	VSENSE low-going threshold to enable COMP large signal gain, percent	Relative to VSENSEreg, COMP = 3 V	−3.25%	−5%	−6.75%
	VSENSE to COMP transconductance, large signal	VSENSE = VSENSEreg – 0.4 V , COMP = 3 V	210	290	370	µS
	VSENSE to COMP transconductance, large signal	VSENSE = VSENSEreg + 0.4 V, COMP = 3 V	210	290	370	µS
	COMP maximum source current	VSENSE = 5 V, COMP = 3 V	−80	−125	−170	µA
R_COMPDCHG	COMP discharge resistance	HVSEN = 5.2 V, COMP = 3 V	1.6	2	2.4	kΩ
I_DODCHG	COMP discharge current during Dropout	VSENSE = 5 V, VINAC = 0.3 V	3.2	4	4.8	µA
V_{LOW_OV}	VSENSE over-voltage threshold, rising	Relative to VSENSEreg	7%	8%	10%
	VSENSE over-voltage hysteresis	Relative to V_{LOW_OV}	−1.5%	−2%	−3%
V_{HIGH_OV}	VSENSE 2nd over-voltage threshold, rising	Relative to VSENSEreg	10.5%	11.3%	14%
SOFT START
V_SSTHR	COMP Soft-Start threshold, falling	VSENSE = 1.5 V	15	23	30	mV
I_SS,FAST	COMP Soft-Start current, fast	SS-state, V_ENAB < VSENSE < VREF/2	−80	−125	−170	µA
I_SS,SLOW	COMP Soft-Start current, slow	SS-state, VREF/2 < VSENSE < 0.88VREF	−11.5	−16	−20	µA
K_EOSS	VSENSE End-of-Soft-Start threshold factor	Percent of VSENSEreg	96.5%	98.3%	99.8%
OUTPUT MONITORING
V_PWMCNTL	HVSEN threshold to PWMCNTL	HVSEN rising	2.35	2.50	2.65	V
I_HVSEN	HVSEN input bias current, high	HVSEN = 3 V		±0.03	±0.5	µA
I_{HV_HYS}	HVSEN hysteresis bias current, low	HVSEN = 2 V	9.2	11.4	14	µA
V_{HV_OV_FLT}	HVSEN threshold to over-voltage fault	HVSEN rising	4.64	4.87	5.1	V
V_{HV_OV_CLR}	HVSEN threshold to over-voltage clear	HVSEN falling	4.45	4.67	4.8
V_{COMP_PHFOFF}	Phase Fail monitoring-disable threshold	COMP falling	0.21	0.225	0.25
V_{COMP_PHFHYS}	Phase Fail monitoring hysteresis	COMP rising		0.051
	PWMCNTL output voltage low	HVSEN = 3 V, I_PWMCNTL = 5 mA, COMP = 0 V		0.2	0.5
t_PHFDLY	Phase Fail filter time to PWMCNTL high	PHB = 5 V, ZCDA switching, ZCDB = 0.5 V, COMP = 3 V	7.9	12	17	ms
I_{PWMCNTL_LEAK}	PWMCNTL leakage current, high	HVSEN = 2 V, PWMCNTL = 15 V		±0.03	±0.5	µA
GATE DRIVE⁽²⁾
	GDA, GDB output voltage, high	I_GDA, I_GDB = −100 mA	11.5	12.4	15	V
	GDA, GDB on-resistance, high	I_GDA, I_GDB = −100 mA		8.8	14	Ω
	GDA, GDB output voltage, low	I_GDA, I_GDB = 100 mA		0.18	0.32	V
	GDA, GDB on-resistance, low	I_GDA, I_GDB = 100 mA		2	3.2	Ω
	GDA, GDB output voltage high, clamped	VCC = 20 V, I_GDA, I_GDB = −5 mA	12	13.5	15	V
	GDA, GDB output voltage high, low VCC	VCC = 12 V, I_GDA, I_GDB = −5 mA	10	10.5	11.5	V
	Rise time	1 V to 9 V, C_LOAD = 1 nF		18	30	ns
	Fall time	9 V to 1 V, C_LOAD = 1 nF		12	25	ns
	GDA, GDB output voltage, UVLO	VCC = 3.0 V, I_GDA, I_GDB = 2.5 mA		100	200	mV
ZERO CURRENT DETECTOR
	ZCDA, ZCDB voltage threshold, falling		0.8	1	1.2	V
	ZCDA, ZCDB voltage threshold, rising		1.5	1.7	1.9
	ZCDA, ZCDB clamp, high	I_ZCDA = +2 mA, I_ZCDB = +2 mA	2.6	3	3.4
	ZCDA, ZCDB clamp, low	I_ZCDA = −2 mA, I_ZCDB = −2 mA	0	−0.2	−0.4
	ZCDA, ZCDB input bias current	ZCDA = 1.4 V, ZCDB = 1.4 V		±0.03	±0.5	µA
	ZCDA, ZCDB delay to GDA, GDB outputs⁽²⁾	From ZCDx input falling to 1 V to respective gate drive output rising 10%		50	100	ns
	ZCDA blanking time⁽³⁾	From GDA rising and GDA falling		100
	ZCDB blanking time⁽³⁾	From GDB rising and GDB falling		100
CURRENT SENSE
	CS input bias current, dual-phase	At rising threshold	−120	−166	−200	µA
	CS current-limit rising threshold, dual-phase	PHB = 5 V	−0.18	−0.2	−0.22	V
	CS current-limit rising threshold, single-phase	PHB = 0 V	−0.149	−0.166	−0.183
	CS current-limit reset falling threshold		−0.003	–0.015	−0.025
	CS current-limit response time⁽²⁾	From CS exceeding threshold−0.05 V to GDx dropping 10%		60	100	ns
	CS blanking time	From GDx rising and falling edges		100		ns
VINAC INPUT
I_VINAC	VINAC input bias current, above brownout	VINAC = 2 V		±0.03	±0.5	µA
V_BODET	VINAC brownout detection threshold	VINAC falling	1.33	1.39	1.44	V
t_BODLY	VINAC brownout filter time	VINAC below the brownout detection threshold for the brownout filter time	340	440	540	ms
V_BOHYS	VINAC brownout threshold hysteresis	VINAC rising	30	62	75	mV
I_BOHYS	VINAC brownout hysteresis current	VINAC = 1 V for > t_BODLY	1.6	2	2.5	µA
V_DODET	VINAC dropout detection threshold	VINAC falling	0.315	0.35	0.38	V
t_DODLY	VINAC dropout filter time	VINAC below the dropout detection threshold for the dropout filter time	3.5	5	7	ms
V_DOCLR	VINAC dropout clear threshold	VINAC rising	0.67	0.71	0.75	V
PULSE-WIDTH MODULATOR
K_T	On-time factor, phases A and B	VSENSE = 5.8 V⁽⁴⁾	3.6	4.0	4.4	µs/V
K_TS	On-time factor, single-phase, A	VSENSE = 5.8 V, PHB = 0 V⁽⁴⁾	7.2	8.0	8.9	µs/V
	Phase B to phase A on-time matching error	VSENSE = 5.8 V		±2%	±6%
	Zero-crossing distortion correction additional on time	COMP = 0.25 V, VINAC = 1 V	1.2	2	2.8	µs
	Zero-crossing distortion correction additional on time	COMP = 0.25 V, VINAC = 0.1 V	12.6	20	29	µs
V_PHBF	PHB threshold falling, to single-phase operation	To GDB output shutdown, VINAC = 1.5 V	0.7	0.8	0.9	V
V_PHBR	PHB threshold rising, to two-phase operation	To GDB output running, VINAC = 1.5 V	0.9	1	1.1	V
T_MIN	Minimum switching period	R_TSET = 133 kΩ⁽⁴⁾	1.7	2.2	3	µs
T_START	PWM restart time	ZCDA = ZCDB = 2 V⁽⁵⁾	165	210	265	µs
THERMAL SHUTDOWN
T_J	Thermal shutdown temperature	Temperature rising⁽⁶⁾		160		°C
T_J	Thermal restart temperature	Temperature falling⁽⁶⁾		140		°C

(1) Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply. If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended. See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.

(2) Refer to Figure 6-13, Figure 6-14, Figure 6-15, and Figure 6-16 of the Typical Characteristics for typical gate drive waveforms.

(3) ZCD blanking times are ensured by design.

(4) Gate drive on-time is proportional to (V_COMP – 0.125 V). The on-time proportionality factor, K_T, scales linearly with the value of R_TSET and is different in two-phase and single-phase modes. The minimum switching period is proportional to R_TSET.

(5) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.

(6) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating temperature is not specified or assured.