SLUSC60B December   2017  – October 2019 UCC28064A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Application
  4. Revision History
  5. Description (Continued)
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Principles of Operation
      2. 8.3.2  Natural Interleaving
      3. 8.3.3  On-Time Control, Maximum Frequency Limiting, Restart Timer and Input Voltage Feed-Forward compensation
      4. 8.3.4  Distortion Reduction
      5. 8.3.5  Zero-Current Detection and Valley Switching
      6. 8.3.6  Phase Management and Light-Load Operation
      7. 8.3.7  Burst Mode Operation
      8. 8.3.8  External Disable
      9. 8.3.9  Improved Error Amplifier
      10. 8.3.10 Soft Start
      11. 8.3.11 Brownout Protection
      12. 8.3.12 Line Dropout Detection
      13. 8.3.13 VREF
      14. 8.3.14 VCC
      15. 8.3.15 System Level Protections
        1. 8.3.15.1 Failsafe OVP - Output Over-voltage Protection
        2. 8.3.15.2 Overcurrent Protection
        3. 8.3.15.3 Open-Loop Protection
        4. 8.3.15.4 VCC Undervoltage Lock-Out (UVLO) Protection
        5. 8.3.15.5 Phase-Fail Protection
        6. 8.3.15.6 CS - Open, TSET - Open and Short Protection
        7. 8.3.15.7 Thermal Shutdown Protection
        8. 8.3.15.8 Fault Logic Diagram
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1  Custom Design With WEBENCH® Tools
        2. 9.2.2.2  Inductor Selection
        3. 9.2.2.3  ZCD Resistor Selection RZA, RZB
        4. 9.2.2.4  HVSEN
        5. 9.2.2.5  Output Capacitor Selection
        6. 9.2.2.6  Selecting RS For Peak Current Limiting
        7. 9.2.2.7  Power Semiconductor Selection (Q1, Q2, D1, D2)
        8. 9.2.2.8  Brownout Protection
        9. 9.2.2.9  Converter Timing
        10. 9.2.2.10 Programming VOUT
        11. 9.2.2.11 Voltage Loop Compensation
      3. 9.2.3 Application Curves
        1. 9.2.3.1 Input Ripple Current Cancellation with Natural Interleaving
        2. 9.2.3.2 Brownout Protection
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Package Option Addendum
    1. 12.1 Packaging Information
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Development Support
        1. 13.1.1.1 Custom Design With WEBENCH® Tools
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Receiving Notification of Documentation Updates
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Overview

Transition mode (TM) control is a popular choice for the boost power factor correction topology at lower power levels. Some advantages of this control method are its lower complexity in achieving high power factor and because lower cost boost diode with higher reverse recovery current specification may be used. In TM control MOSFET is turned on always when no current is flowing into diode. Interleaved Transition Mode Control retains this benefit and generally extends the applicability up to much higher power levels while simultaneously conferring the interleaving benefits of reduced input and output ripple current and system thermal optimization.

In UCC28064A, burst mode was introduced respect its predecessor (UCC28063) to achieve higher efficiency in light load conditions. Input voltage feed-forward and threshold adjustment is also available to ensure the user can optimize performance across line and load conditions. When operating single phase on time of the switching phase is doubled with the purpose of compensating the missing power from the not switching phase. In this way for the same COMP value the converter should provide the same output power regardless if operating single phase mode or dual phase mode. Unfortunately this is not always the case. Component variations and MOSFETs turn-off delay can lead to big differences (for the same COMP voltage) in the output power delivery. The Phase Management and Light-Load Operation section will discuss some ways to deal with the variations.

Line voltage feed-forward compensation provides several benefits: it maintains constant bandwidth of the control loop versus line voltage variation, avoids high current in the MOSFETs, inductors, and line filter when line transitions from low to high happens, and helps to keep simple Phase Management control because the COMP pin voltage is almost proportional to Load. Burst Mode enables high efficiency at light load and soft-on and soft-off in burst mode reduces risk of audible noise. The optimal load current at which the converter should enter burst mode can be different for different input voltages. These thresholds can be customized by the user.

Interleaving control and phase management facilitates high efficiency 80+ and Energy Star designs with reduced input and output ripple. The Natural Interleaving method allows TM operation and achieves 180 degrees between the phases by On-time management. Moreover Natural interleaving method does not rely on tight tolerance requirements on the inductors. Negative current sensing is implemented on the total input current instead of just the MOSFET current which prevents MOSFET switching during inrush surges or in any mode where the inductor current may enter in continuous conduction mode (CCM). This prevents reverse recovery conduction events between the MOSFET and output rectifier.

Independent output voltage sense circuits with their separate fault management behaviors provide a high degree of redundancy against PFC stage over-voltage. Brownout, over voltage protection on HVSEN pin (HVSENSE OV), under voltage lockout (UVLO), and device over-temperature faults will all cause a complete Soft-Start cycle. Other faults such as short duration AC Drop-Out, minor over-voltage or cycle-by-cycle over-current cause a live recovery process to initiate by pulling down the COMP pin or by terminating the pulses early.

The error amplifier transconductance is designed to allow smaller compensation components and optimum transient response for large changes in line or load. The Soft-Start process is carefully optimized. A complete Soft-Start is implemented. It is dependent on the output voltage sense to speed up start-up from low AC line and to minimize the effect of excessive capacitance on the COMP pin during start-up into no-load. If some faults events are triggered COMP pin is fast pulled down to zero. This complete discharge of COMP aids with preventing excessive currents on recovery from an AC Brown-Out event.