SLUSBW3D March 2014 – December 2017 UCC28630 , UCC28631 , UCC28632 , UCC28633 , UCC28634
PRODUCTION DATA.
The typical application circuit of Figure 39 may be redrawn as a simplified equivalent circuit as shown in Figure 45. In this equivalent circuit, the capacitor C_{P} is the total parasitic capacitance (MOSFET C_{oss}, transformer capacitance, etc), and resistance R_{WAKE} is the effective internal resistance of the UCC24650 WAKE pin to GND pin when the internal WAKE pull-down is active (see UCC24650 detailed datasheet specifications).
If all the elements on the primary and secondary of the transformer are referred to the bias winding, this can be further simplified as in Figure 46.
Thus, knowing L_{P} and C_{P}, the power stage impedance Z_{LC(bias)} (reflected to the bias winding) may be calculated from Equation 66, and the effective wake resistance can be referred to the bias winding using Equation 67. The wake pulse amplitude can be calculated from Equation 68. If C_{P} is not known, it can be measured by observing the resonant ring period at the primary drain node, T_{RES}, and calculating C_{P} from Equation 69. Worst case values should be used to estimate the worst case minimum wake pulse amplitude at the VSENSE pin. It should also be noted that any filter cap on the VSENSE pin (including internal parasitic pin capacitance) adds an RC filter in conjunction with the Thevenin resistance of the VSENSE divider, R_{T}, R_{B}; this delays and further attenuate the wake pulse amplitude. Additionally, the internal wake comparator requires some over-drive to trip, and exhibits propagation delay that depends on the amount of overdrive. So some margin should be allowed in the wake pulse amplitude to ensure that the minimum wake pulse can adequately overdrive the internal wake comparator. A margin of at least 20% over the threshold V_{SENSE(wake)} is recommended.
If the worst case wake pulse amplitude is too low, then the UCC24650 WAKE output can be augmented with an external PNP circuit Q1, R1 and R2, as shown in Figure 40. This circuit reduces the effective wake resistance to ground, so that a larger proportion of the output voltage appears across the transformer secondary pins when the UCC24650 WAKE activates.
Using the UCC28630EVM-572, (TI Literature Number SLUUAX9) circuit parameters from Figure 44, the nominal wake pulse amplitude at the VSENSE pin can be estimated. Of course, the rectifying diode D7 in Figure 44 would need to be relocated to return end of the secondary winding (pins 10, 11) to allow UCC24650 to be deployed.
From observation of the DCM ringing period, the period T_{RES} was found to be 1.138 μs. From Equation 69, C_{P} is estimated:
From Equation 66, the power circuit impedance is:
The WAKE pin resistance R_{WAKE} can be determined form the UCC24650 datasheet; for now a nominal value of 400 Ω is assumed. Referred to the bias winding (scaled by (N_{B}/N_{S})^{2}), this becomes 178 Ω. Similarly Δ_{WAKE%} can be determined from the UCC24650 datasheet; for now, a value of 97% is assumed. From Equation 68, the wake pulse amplitude can be calculated:
In this case, the VSENSE wake pulse amplitude would be insufficient to trip the internal wake comparator. If the power stage had higher L_{P}, or lower C_{P}, a larger wake pulse would be produced.
Alternatively, the effective wake resistance R_{WAKE} may be reduced by adding the PNP circuit per Figure 40. This has been verified using Q1 = FMMTA92 PNP transistor, R1= 100 Ω and R2 = 2.2 kΩ. A wake pulse amplitude of almost 2 V_{PK} was produced at the VSENSE pin, giving generous margin to the internal threshold V_{SENSE(wake)}. The observed waveforms are shown in Figure 47 for a worst case 0% to 100% (65 W) load transient (where the PWM is at F_{MIN}). The PWM is re-activated when V_{OUT} has dropped by ~3%, rather waiting for the next timed wake-up (~5 ms later).
Figure 48 shows a zoomed waveform of the wake pulsing ringing as measured on the bias winding. It can be seen that the peak level is approximately 3 V_{PK}, which would produce a pulse of approximately 1.8 V at the VSENSE pin (scaled by VSENSE divider resistors R_{T} and R_{B}). As noted in Test and Debug Recommendations, the VSENSE pin should never be directly probed, doing so affects the regulation setpoint.