SLUSDV5B October   2019  – April 2020 UCC5304

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Rising and Falling Time
    2. 7.2 Power-up UVLO Delay to OUTPUT
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN pin Input Filter
        2. 9.2.2.2 Estimating Junction Temperature
        3. 9.2.2.3 Selecting VCCI and VDD Capacitors
          1. 9.2.2.3.1 Selecting a VCCI Capacitor
          2. 9.2.2.3.2 Selecting a VDD Capacitor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.10 Switching Characteristics

VVCCI = 3.3 V or 5.5 V, 0.1-µF capacitor from VCCI to GND, VVDD = 12 V, 1-µF capacitor from VDD and VSS, load capacitance COUT = 0 pF, TJ = –40°C to +125°C, unless otherwise noted(1).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tRISE Output rise time, see Figure 17 CVDD = 10 µF, COUT = 1.8 nF,
VVDD = 12 V, f = 1 kHz		 5 16 ns
tFALL Output fall time, see Figure 17 CVDD = 10 µF, COUT = 1.8 nF ,
VVDD = 12 V, f = 1 kHz		 6 12 ns
tPWmin Minimum input pulse width that passes to output,
see and 		Output does not change the state if input signal less than tPWmin 10 20 ns
tPDHL Propagation delay at falling edge, see INx high threshold, VINH, to 10% of the output 28 40 ns
tPDLH Propagation delay at rising edge, see INx low threshold, VINL, to 90% of the output 28 40 ns
tPWD Pulse width distortion in each channel, see |tPDLH – tPDHL| 5.5 ns
tVCCI+ to OUT VCCI Power-up Delay Time: UVLO Rise to OUT,
See Figure 18 		IN tied to VCCI 40 59 µs
tVDD+ to OUT VDD Power-up Delay Time: UVLO Rise to OUT
See Figure 19 		INtied to VCCI 22 35
|CMH| High-level common-mode transient immunity (See ) Slew rate of GND vs. VSS, IN is tied to GND or VCCI; VCM=1000 V; 100 V/ns
|CML| Low-level common-mode transient immunity (See ) Slew rate of GND vs. VSS, IN is tied to GND or VCCI; VCM=1000 V; 100
(1) Parameters that has only typical values, are not production tested and guaranteed by design.