SLUSDV5B October   2019  – April 2020 UCC5304

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Typical Application
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Rising and Falling Time
    2. 7.2 Power-up UVLO Delay to OUTPUT
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input Stage
      3. 8.3.3 Output Stage
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing IN pin Input Filter
        2. 9.2.2.2 Estimating Junction Temperature
        3. 9.2.2.3 Selecting VCCI and VDD Capacitors
          1. 9.2.2.3.1 Selecting a VCCI Capacitor
          2. 9.2.2.3.2 Selecting a VDD Capacitor
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Component Placement Considerations
      2. 11.1.2 Grounding Considerations
      3. 11.1.3 High-Voltage Considerations
      4. 11.1.4 Thermal Considerations
    2. 11.2 Layout Example
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6.9 Electrical Characteristics

VVCCI = 3.3 V or 5.0 V, 0.1-µF capacitor from VCCI to GND and 1uF capacitor from VDD to VSS, VVDD = 12 V, 1-µF capacitor from VDD to VSS, TA = –40°C to +125°C, unless otherwise noted(1)(2).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENTS
IVCCI VCCI quiescent current VIN = 0 V 1.5 2.0 mA
IVDD VDD quiescent current VIN = 0 V, 1.0 1.8 mA
IVCCI VCCI operating current (f = 500 kHz) operating current 2.5 mA
IVDD VDD operating current (f = 500 kHz) operating current COUT = 100 pF,
VVDD = 12 V		 2.5 mA
VCC SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVCCI_ON UVLO Rising threshold 2.55 2.7 2.85 V
VVCCI_OFF UVLO Falling threshold 2.35 2.5 2.65 V
VVCCI_HYS UVLO Threshold hysteresis 0.2 V
VDD SUPPLY VOLTAGE UNDERVOLTAGE THRESHOLDS
VVDD UVLO Rising threshold 5.0 5.5 5.9 V
VVDD_OFF UVLO Falling threshold 4.7 5.2 5.6 V
VVDD_HYS UVLO Threshold hysteresis 0.3 V
IN
VINH Input high threshold voltage 1.6 1.8 2 V
VINL Input low threshold voltage 0.8 1 1.25 V
VIN_HYS Input threshold hysteresis 0.8 V
OUTPUT
IO+ Peak output source current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 4 A
IO- Peak output sink current CVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement 6 A
ROH Output resistance at high state IOUT = –10 mA, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Switching Characteristics and Output Stage for more details. 5 Ω
ROL Output resistance at low state IOUT = 10 mA 0.55 Ω
VOH Output voltage at high state VVDD = 12 V, IOUT = –10 mA 11.95 V
VOL Output voltage at low state VVDD = 12 V, IOUT = 10 mA 5.5 mV
VOAPD Driver output (VOUT) active pull down VVDD, IOUT = 200 mA 1.75 2.1 V
(1) Current direction in the testing conditions are defined to be positive into the pin and negative out of the specified terminal (unless otherwise noted).
(2) Parameters that has only typical values, are not production tested and guaranteed by design.