JAJSCA2B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ADS89xxB内蔵の機能によりシステムを簡単に設計
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. Sample-and-Hold Circuit
        2. Internal Oscillator
        3. ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. Protocols for Configuring the Device
        2. Protocols for Reading From the Device
          1. Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. SPI-Compatible Protocols with Bus Width Options
          3. Source-Synchronous (SRC) Protocols
            1. Output Clock Source Options with SRC Protocols
            2. Bus Width Options With SRC Protocols
            3. Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. Single Device: All multiSPI Options
        2. Single Device: Minimum Pins for a Standard SPI Interface
        3. Multiple Devices: Daisy-Chain Topology
        4. Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. Charge-Kickback Filter
        2. Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Data Transfer Frame

A data transfer frame between the device and the host controller is bounded between a CS falling edge and the subsequent CS rising edge. The host controller can initiate a data transfer frame (as shown in Figure 43) at any time irrespective of the status of the CONVST signal; however, the data read during such a data transfer frame is a function of relative timing between the CONVST and CS signals.

ADS8910B ADS8912B ADS8914B data_transfer_frame_bas707.gifFigure 43. Data Transfer Frame

For this discussion, assume that the CONVST signal remains low.

A typical data transfer frame F follows this order:

  1. The host controller pulls CS low to initiate a data transfer frame. On the CS falling edge:
    • RVS goes low, indicating the beginning of the data transfer frame.
    • The SCLK counter is reset to 0.
    • The device takes control of the data bus. As shown in Figure 43, the 22-bit contents of the output data word (see Figure 41) are loaded in to the 22-bit output data register (ODR; see Figure 37).
    • The 22-bit input data register (IDR; see Figure 37) is reset to 000000h, corresponding to a NOP command.
  2. During the frame, the host controller provides clocks on the SCLK pin. Inside the device:
    • For each SCLK capture edge, the SCLK counter is incremented and the data bit received on the SDI pin is shifted in to the IDR.
    • For each launch edge of the output clock (SCLK in this case), ODR data are shifted out on the selected SDO-x pins.
    • The status of the RVS pin depends on the output protocol selection (see the Protocols for Reading From the Device section).
  3. The host controller pulls CS high to end the data transfer frame. On the CS rising edge:
    • The SDO-x pins go to Hi-Z.
    • RVS goes high (after a delay of td_CSRDY_r).
    • As illustrated in Figure 43, the 22-bit contents of the IDR are transferred to the command processor (see Figure 37) for decoding and further action.

After pulling CS high, the host controller monitors for a low-to-high transition on the RVS pin, or waits for the td_CSRDY_r time (see the Switching Characteristics table) to elapse before initiating a new operation (data transfer or conversion). The delay, td_CSRDY_r, for any data transfer frame F varies based on the data transfer operation executed in frame F.

At the end of data transfer frame F:

  • If the SCLK counter is < 22, then the IDR captured less than 22 bits from the SDI. In this case, the device treats frame F as a short command frame. At the end of a short command frame, the IDR is not updated and the device treats the frame as a no operation (NOP) command.
  • If the SCLK counter = 22, then the IDR captured exactly 22 bits from SDI. In this case, the device treats the frame F as a optimal command frame. At the end of an optimal command frame, the command processor decodes the 22-bit contents of the IDR as a valid command word.
  • If the SCLK counter > 22, then the IDR captured more than 22 bits from the SDI; however, only the last 22 bits are retained. In this case, the device treats frame F as a long command frame. At the end of a long command frame, the command processor treats the 22-bit contents of the IDR as a valid command word. There is no restriction on the maximum number of clocks that can be provided within any data transfer frame F. However, as explained above, make sure that the last 22 bits shifted into the device before the CS rising edge constitute the desired command.

In a short command frame, the write operation to the device is invalidated; however, the output data bits transferred during the short command frame are still valid output data. Therefore, the host controller can use such shorter data transfer frames to read only the required number of MSB bits from the 22-bit output data word. As shown in Figure 41, an optimal read frame for the ADS891xB devices must read only the 18 MSB bits of the output data word. The length of an optimal read frame depends on the output protocol selection; see the Protocols for Reading From the Device section for more details.


The previous example shows data-read and data-write operations synchronous to the external clock provided on the SCLK pin.

However, the device also supports data read operation synchronous to the internal clock; see the Protocols for Reading From the Device section for more details. In this case, while the ODR contents are shifted on the SDO (or SDOs) on the launch edge of the internal clock, the device continues to capture the SDI data into the IDR (and increment the SCLK counter) on SCLK capture edges.