JAJSCA2B June 2016 – January 2018 ADS8910B , ADS8912B , ADS8914B
PRODUCTION DATA.
The device features nine configuration registers, mapped as described in Table 10.
ADDRESS | REGISTER NAME | REGISTER DESCRIPTION |
---|---|---|
004h | PD_CNTL | Low-power modes control |
008h | SDI_CNTL | SDI input protocol selection |
00Ch | SDO_CNTL | SDO output protocol selection |
010h | DATA_CNTL | Output data word configuration |
014h | PATN_LSB | Eight least significant bits (LSB) of the output pattern |
015h | PATN_MID | Eight middle bits of the output pattern |
016h | PATN_MSB | Four most significant bits (MSB) of the output pattern |
020h | OFST_CAL | Offset calibration |
030h | REF_MRG | Reference margin |