JAJSCA2B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B


  1. 特長
  2. アプリケーション
  3. 概要
    1.     Device Images
      1.      ADS89xxB内蔵の機能によりシステムを簡単に設計
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. Sample-and-Hold Circuit
        2. Internal Oscillator
        3. ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. Protocols for Configuring the Device
        2. Protocols for Reading From the Device
          1. Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. SPI-Compatible Protocols with Bus Width Options
          3. Source-Synchronous (SRC) Protocols
            1. Output Clock Source Options with SRC Protocols
            2. Bus Width Options With SRC Protocols
            3. Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. Single Device: All multiSPI Options
        2. Single Device: Minimum Pins for a Standard SPI Interface
        3. Multiple Devices: Daisy-Chain Topology
        4. Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. Charge-Kickback Filter
        2. Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報



Data Transfer Protocols

This device family features a multiSPI digital interface that allows the host controller to operate at slower SCLK speeds and still achieve the required throughput and response time. The multiSPI digital interface module offers three options to reduce the SCLK speed required for data transfer:

  • Increase the width of the output data bus.
  • Enable double data rate (DDR) transfer.
  • Extended data transfer window, as shown in Figure 46.

These three options can be combined to achieve further reduction in SCLK speed.

There are various factors that limit the maximum SCLK frequency in a system.

Figure 47 shows the delays in the communication channel between the host controller and the device in a typical serial communication.

ADS8910B ADS8912B ADS8914B ai_spi_delays_sbas629.gifFigure 47. Delays in Serial Communication

For example, if tpcb_CK and tpcb_SDO are the delays introduced by the printed circuit board (PCB) traces for the serial clock and SDO signals, td_CKDO is the clock-to-data delay of the device, td_ISO is the propagation delay introduced by the digital isolator, and tsu_h is the setup time specification of the host controller, then the total delay in the path is given by Equation 11:

Equation 11. ADS8910B ADS8912B ADS8914B ai_eq_td_total_serial_sbas629.gif

In a standard SPI protocol, the host controller and the device launch and capture data bits on alternate SCLK edges. Therefore, the td_total_serial delay must be kept to less than half of the SCLK duration. Equation 12 shows the fastest clock allowed by the SPI protocol:

Equation 12. ADS8910B ADS8912B ADS8914B ai_eq_fclk-SPI_sbas629.gif

Larger values of the td_total_serial delay restricts the maximum SCLK speed for the SPI protocol, resulting in higher read and response times, and can possibly limit the throughput.

Figure 48 shows a delay (td_delcap) introduced in the capture path (inside the host controller).

ADS8910B ADS8912B ADS8914B ai_spi_delays_delcap_sbas707.gifFigure 48. Delayed Capture

The total delay in the path modifies to Equation 13:

Equation 13. ADS8910B ADS8912B ADS8914B ai_eq_td_total_serial_sbas707.gif

This reduction in total delay allows the SPI protocol to operate at higher clock speeds.

The multiSPI digital interface module offers two additional options to remove the restriction on the SCLK speed:

  • Early data launch (EDL) mode of operation
  • In EDL mode, the device launches the output data on SDO-x pin (or pins) half a clock earlier compared to the standard SPI protocol. Therefore, Equation 12 modifies to Equation 14:

    Equation 14. ADS8910B ADS8912B ADS8914B ai_eq_fclk-SPI_sbas707.gif

    The reduction in total delay allows the serial interface to operate at higher clock speeds.

  • ADC-Clock-Master (source-synchronous) mode of operation
  • As illustrated in Figure 49, in ADC-Clock-Master mode, the device provides a synchronous output clock (on the RVS pin) along with the output data (on the SDO-x pins).

    ADS8910B ADS8912B ADS8914B ai_srcsync_delays_sbas629.gifFigure 49. Delays in ADC-Clock-Master (Source-Synchronous) Mode

    For negligible values of toff_STRDO, the total delay in the path for a source-synchronous data transfer, is given by Equation 15:

    Equation 15. ADS8910B ADS8912B ADS8914B ai_eq_td_total_srcsync_sbas629.gif

    As shown by the difference between Equation 11 and Equation 15, using ADC-Clock-Master mode completely eliminates the effect of isolator delays (td_ISO) and clock-to-data delays (td_CKDO); typically, the largest contributors in the overall delay computation.

    Furthermore, the actual values of tpcb_RVS and tpcb_SDO do not matter. In most cases, the td_total_srcsync delay can be kept at a minimum by routing the RVS and SDO lines together on the PCB. Therefore, the ADC-Clock-Master mode allows the data transfer between the host controller and the device to operate at much higher SCLK speeds. For more information about using ADC-Clock-Master to mode to achieve fast SCLK speeds, with an isolated interface or high routing delays, see Optimizing Data Transfer on High-Resolution, High Throughput Data Converters. Zone 2 data transfer also enables longer quiet time for analog input settling, and is discussed in Improving Input Settling for Precision Data Converters.