SPRSP58 June   2022 AM623 , AM625

ADVANCE INFORMATION  

  1. Features
  2. Applications
  3. Description
    1. 3.1 Functional Block Diagram
  4. Revision History
  5. Device Comparison
    1. 5.1 Related Products
  6. Terminal Configuration and Functions
    1. 6.1 Pin Diagrams
    2. 6.2 Pin Attributes
      1.      11
      2.      12
    3. 6.3 Signal Descriptions
      1.      14
      2. 6.3.1  CPSW3G
        1. 6.3.1.1 MAIN Domain
          1.        17
          2.        18
          3.        19
          4.        20
      3. 6.3.2  CPTS
        1. 6.3.2.1 MAIN Domain
          1.        23
      4. 6.3.3  CSI
        1. 6.3.3.1 MAIN Domain
          1.        26
      5. 6.3.4  DDRSS
        1. 6.3.4.1 MAIN Domain
          1.        29
      6. 6.3.5  DSS
        1. 6.3.5.1 MAIN Domain
          1.        32
      7. 6.3.6  ECAP
        1. 6.3.6.1 MAIN Domain
          1.        35
          2.        36
          3.        37
      8. 6.3.7  Emulation and Debug
        1. 6.3.7.1 MAIN Domain
          1.        40
        2. 6.3.7.2 MCU Domain
          1.        42
      9. 6.3.8  EPWM
        1. 6.3.8.1 MAIN Domain
          1.        45
          2.        46
          3.        47
          4.        48
      10. 6.3.9  EQEP
        1. 6.3.9.1 MAIN Domain
          1.        51
          2.        52
          3.        53
      11. 6.3.10 GPIO
        1. 6.3.10.1 MAIN Domain
          1.        56
          2.        57
        2. 6.3.10.2 MCU Domain
          1.        59
      12. 6.3.11 GPMC
        1. 6.3.11.1 MAIN Domain
          1.        62
      13. 6.3.12 I2C
        1. 6.3.12.1 MAIN Domain
          1.        65
          2.        66
          3.        67
          4.        68
        2. 6.3.12.2 MCU Domain
          1.        70
        3. 6.3.12.3 WKUP Domain
          1.        72
      14. 6.3.13 MCAN
        1. 6.3.13.1 MAIN Domain
          1.        75
        2. 6.3.13.2 MCU Domain
          1.        77
          2.        78
      15. 6.3.14 MCASP
        1. 6.3.14.1 MAIN Domain
          1.        81
          2.        82
          3.        83
      16. 6.3.15 MCSPI
        1. 6.3.15.1 MAIN Domain
          1.        86
          2.        87
          3.        88
        2. 6.3.15.2 MCU Domain
          1.        90
          2.        91
      17. 6.3.16 MDIO
        1. 6.3.16.1 MAIN Domain
          1.        94
      18. 6.3.17 MMC
        1. 6.3.17.1 MAIN Domain
          1.        97
          2.        98
          3.        99
      19. 6.3.18 OLDI
        1. 6.3.18.1 MAIN Domain
          1.        102
      20. 6.3.19 OSPI
        1. 6.3.19.1 MAIN Domain
          1.        105
      21. 6.3.20 Power Supply
        1.       107
      22. 6.3.21 PRU_ICSS
        1. 6.3.21.1 MAIN Domain
          1.        110
          2.        111
      23. 6.3.22 Reserved
        1.       113
      24. 6.3.23 System and Miscellaneous
        1. 6.3.23.1 Boot Mode Configuration
          1. 6.3.23.1.1 MAIN Domain
            1.         117
        2. 6.3.23.2 Clock
          1. 6.3.23.2.1 MCU Domain
            1.         120
          2. 6.3.23.2.2 WKUP Domain
            1.         122
        3. 6.3.23.3 System
          1. 6.3.23.3.1 MAIN Domain
            1.         125
          2. 6.3.23.3.2 MCU Domain
            1.         127
          3. 6.3.23.3.3 WKUP Domain
            1.         129
        4. 6.3.23.4 VMON
          1.        131
      25. 6.3.24 TIMER
        1. 6.3.24.1 MAIN Domain
          1.        134
        2. 6.3.24.2 MCU Domain
          1.        136
        3. 6.3.24.3 WKUP Domain
          1.        138
      26. 6.3.25 UART
        1. 6.3.25.1 MAIN Domain
          1.        141
          2.        142
          3.        143
          4.        144
          5.        145
          6.        146
          7.        147
        2. 6.3.25.2 MCU Domain
          1.        149
        3. 6.3.25.3 WKUP Domain
          1.        151
      27. 6.3.26 USB
        1. 6.3.26.1 MAIN Domain
          1.        154
          2.        155
    4. 6.4 Pin Connectivity Requirements
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Operating Performance Points
    6. 7.6  Power Consumption Summary
    7. 7.7  Electrical Characteristics
      1. 7.7.1 I2C Open-Drain, and Fail-Safe (I2C OD FS) Electrical Characteristics
      2. 7.7.2 Fail-Safe Reset (FS RESET) Electrical Characteristics
      3. 7.7.3 High-Frequency Oscillator (HFOSC) Electrical Characteristics
      4. 7.7.4 SDIO Electrical Characteristics
      5. 7.7.5 LVCMOS Electrical Characteristics
      6. 7.7.6 CSI Electrical Characteristics
      7. 7.7.7 USB2PHY Electrical Characteristics
      8. 7.7.8 DDR Electrical Characteristics
    8. 7.8  VPP Specifications for One-Time Programmable (OTP) eFuses
      1. 7.8.1 Recommended Operating Conditions for OTP eFuse Programming
      2. 7.8.2 Hardware Requirements
      3. 7.8.3 Programming Sequence
      4. 7.8.4 Impact to Your Hardware Warranty
    9. 7.9  Thermal Resistance Characteristics
      1. 7.9.1 Thermal Resistance Characteristics for ALW and AMC Package
    10. 7.10 Timing and Switching Characteristics
      1. 7.10.1 Timing Parameters and Information
      2. 7.10.2 Power Supply Requirements
        1. 7.10.2.1 Power Supply Slew Rate Requirement
        2. 7.10.2.2 Power Supply Sequencing
          1. 7.10.2.2.1 Power-Up Sequencing
          2. 7.10.2.2.2 Power-Down Sequencing
      3. 7.10.3 System Timing
        1. 7.10.3.1 Reset Timing
        2. 7.10.3.2 Error Signal Timing
        3. 7.10.3.3 Clock Timing
      4. 7.10.4 Clock Specifications
        1. 7.10.4.1 Input Clocks / Oscillators
          1. 7.10.4.1.1 MCU_OSC0 Internal Oscillator Clock Source
            1. 7.10.4.1.1.1 Load Capacitance
            2. 7.10.4.1.1.2 Shunt Capacitance
          2. 7.10.4.1.2 MCU_OSC0 LVCMOS Digital Clock Source
          3. 7.10.4.1.3 WKUP_LFOSC0 Internal Oscillator Clock Source
          4. 7.10.4.1.4 WKUP_LFOSC0 Not Used
        2. 7.10.4.2 Output Clocks
        3. 7.10.4.3 PLLs
      5. 7.10.5 Peripherals
        1. 7.10.5.1  CPSW3G
          1. 7.10.5.1.1 CPSW3G MDIO Timing
          2. 7.10.5.1.2 CPSW3G RMII Timing
          3. 7.10.5.1.3 CPSW3G RGMII Timing
        2. 7.10.5.2  CPTS
        3. 7.10.5.3  DDRSS
        4. 7.10.5.4  DSS
        5. 7.10.5.5  ECAP
        6. 7.10.5.6  Emulation and Debug
          1. 7.10.5.6.1 Trace
          2. 7.10.5.6.2 JTAG
        7. 7.10.5.7  EPWM
        8. 7.10.5.8  EQEP
        9. 7.10.5.9  GPIO
        10. 7.10.5.10 GPMC
          1. 7.10.5.10.1 GPMC and NOR Flash — Synchronous Mode
          2. 7.10.5.10.2 GPMC and NOR Flash — Asynchronous Mode
          3. 7.10.5.10.3 GPMC and NAND Flash — Asynchronous Mode
        11. 7.10.5.11 I2C
          1. 7.10.5.11.1 Timing Requirements for I2C Input Timings
        12. 7.10.5.12 MCAN
        13. 7.10.5.13 MCASP
        14. 7.10.5.14 MCSPI
          1. 7.10.5.14.1 MCSPI — Controller Mode
          2. 7.10.5.14.2 MCSPI — Peripheral Mode
        15. 7.10.5.15 MMCSD
          1. 7.10.5.15.1 MMC0 - eMMC/SD/SDIO Interface
            1. 7.10.5.15.1.1  Legacy SDR Mode
            2. 7.10.5.15.1.2  High Speed SDR Mode
            3. 7.10.5.15.1.3  HS200 Mode
            4. 7.10.5.15.1.4  Default Speed Mode
            5. 7.10.5.15.1.5  High Speed Mode
            6. 7.10.5.15.1.6  UHS–I SDR12 Mode
            7. 7.10.5.15.1.7  UHS–I SDR25 Mode
            8. 7.10.5.15.1.8  UHS–I SDR50 Mode
            9. 7.10.5.15.1.9  UHS–I DDR50 Mode
            10. 7.10.5.15.1.10 UHS–I SDR104 Mode
          2. 7.10.5.15.2 MMC1/MMC2 - SD/SDIO Interface
            1. 7.10.5.15.2.1 Default Speed Mode
            2. 7.10.5.15.2.2 High Speed Mode
            3. 7.10.5.15.2.3 UHS–I SDR12 Mode
            4. 7.10.5.15.2.4 UHS–I SDR25 Mode
            5. 7.10.5.15.2.5 UHS–I SDR50 Mode
            6. 7.10.5.15.2.6 UHS–I DDR50 Mode
            7. 7.10.5.15.2.7 UHS–I SDR104 Mode
        16. 7.10.5.16 OLDI
          1. 7.10.5.16.1 OLDI0 Switching Characteristics
        17. 7.10.5.17 OSPI
          1. 7.10.5.17.1 OSPI0 PHY Mode
            1. 7.10.5.17.1.1 OSPI0 With PHY Data Training
            2. 7.10.5.17.1.2 OSPI0 Without Data Training
              1. 7.10.5.17.1.2.1 OSPI0 PHY SDR Timing
              2. 7.10.5.17.1.2.2 OSPI0 PHY DDR Timing
          2. 7.10.5.17.2 OSPI0 Tap Mode
            1. 7.10.5.17.2.1 OSPI0 Tap SDR Timing
            2. 7.10.5.17.2.2 OSPI0 Tap DDR Timing
        18. 7.10.5.18 PRU_ICSS
          1. 7.10.5.18.1 PRU_ICSSM Programmable Real-Time Unit (PRU)
            1. 7.10.5.18.1.1 PRU_ICSSM PRU Direct Output Mode Timing
            2. 7.10.5.18.1.2 PRU_ICSSM PRU Parallel Capture Mode Timing
            3. 7.10.5.18.1.3 PRU_ICSSM PRU Shift Mode Timing
          2. 7.10.5.18.2 PRU_ICSSM Industrial Ethernet Peripheral (IEP)
            1. 7.10.5.18.2.1 PRU_ICSSM IEP Timing
          3. 7.10.5.18.3 PRU_ICSSM Universal Asynchronous Receiver Transmitter (UART)
            1. 7.10.5.18.3.1 PRU_ICSSM UART Timing
          4. 7.10.5.18.4 PRU_ICSSM Enhanced Capture Peripheral (ECAP)
            1. 7.10.5.18.4.1 PRU_ICSSM ECAP Timing
        19. 7.10.5.19 Timers
        20. 7.10.5.20 UART
        21. 7.10.5.21 USB
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Processor Subsystems
      1. 8.2.1 Arm Cortex-A53 Subsystem
      2. 8.2.2 Arm Cortex-M4F
      3. 8.2.3 Device and Power Manager
    3. 8.3 Accelerators and Coprocessors
      1. 8.3.1 PRU_ICSS
    4. 8.4 Other Subsystems
      1. 8.4.1 Peripherals
        1. 8.4.1.1  MCSPI
        2. 8.4.1.2  Dual Date Rate (DDR) External Memory Interface (DDRSS)
        3. 8.4.1.3  ECAP
        4. 8.4.1.4  EPWM
        5. 8.4.1.5  GPIO
        6. 8.4.1.6  GPMC
        7. 8.4.1.7  I2C
        8. 8.4.1.8  MCAN
        9. 8.4.1.9  OSPI
        10. 8.4.1.10 UART
  9. Applications, Implementation, and Layout
    1. 9.1 Device Connection and Layout Fundamentals
      1. 9.1.1 Power Supply Decoupling and Bulk Capacitors
        1. 9.1.1.1 Power Supply Mapping
        2. 9.1.1.2 Power Distribution Network Implementation Guidance
      2. 9.1.2 External Oscillator
      3. 9.1.3 JTAG and EMU
      4. 9.1.4 Reset
      5. 9.1.5 Unused Pins
      6. 9.1.6 Hardware Design Guide
    2. 9.2 Peripheral- and Interface-Specific Design Information
      1. 9.2.1 DDR Board Design and Layout Guidelines
      2. 9.2.2 OSPI/QSPI/SPI Board Design and Layout Guidelines
        1. 9.2.2.1 No Loopback, Internal PHY Loopback, and Internal Pad Loopback
        2. 9.2.2.2 External Board Loopback
        3. 9.2.2.3 DQS (only available in Octal SPI devices)
      3. 9.2.3 USB VBUS Design Guidelines
      4. 9.2.4 System Power Supply Monitor Design Guidelines
      5. 9.2.5 High Speed Differential Signal Routing Guidance
      6. 9.2.6 External Capacitors
      7. 9.2.7 Thermal Solution Guidance
  10. 10Device and Documentation Support
    1. 10.1 Device Nomenclature
      1. 10.1.1 Standard Package Symbolization
      2. 10.1.2 Device Naming Convention
    2. 10.2 Tools and Software
    3. 10.3 Documentation Support
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  11. 11Mechanical, Packaging, and Orderable Information
    1. 11.1 Packaging Information

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ(パッケージ|ピン)
  • ALW|425
サーマルパッド・メカニカル・データ
発注情報

Features

Processor Cores:

  • Up to Quad 64-bit Arm® Cortex®-A53 microprocessor subsystem at up to 1.4 GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm® Cortex®-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device and Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 200-MHz pixel clock support with Independent PLL for each display
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500 Mpixels/sec
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL 3.x/2.0/1.1 + Extensions, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device and Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
    • Max addressable range
      • 8GBytes with DDR4
      • 4GBytes with LPDDR4

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TUV SUD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TUV SUD planned
  • AEC-Q100 qualified

Security:

  • Hardware Security Module
    • Dedicated dual-core Arm Cortex-M4F Security co-processor with 426KB RAM for key and security management, with dedicated device level interconnect for security
    • Dedicated security DMA and IPC subsystem for isolated processing
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 Bits key sizes
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone® based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-Fly encryption support for OSPI interface in XIP mode

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit running up to 333 MHz and Industrial Communication Subystem (PRU-ICSS)
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU with SECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory with SECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of 30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection
    • Trace over USB supported

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Secure Digital® (SD®) (4b+4b+8b) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with 166-MHz DDR / 200-MHz SDR
    • Support for Serial NAND and Serial NOR flash devices
    • Up to 4 CS supported
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm technology
  • 13 mm x 13 mm, 0.5-mm pitch, 425-pin FCCSP BGA (ALW)
  • 17.2 mm x 17.2 mm, 0.8-mm pitch, 441-pin FCBGA (AMC)