製品詳細

Arm CPU 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53 Arm MHz (Max.) 1400 Co-processor(s) 1 Arm Cortex-M4F CPU 64-bit Display type MIPI DPI, OLDI Protocols Ethernet, TSN Ethernet MAC 2-Port 10/100/1000 Hardware accelerators PRU-SS Features Vision Analytics Operating system Linux Security Secure boot Rating Catalog Operating temperature range (C) -40 to 105, 0 to 95
Arm CPU 1 Arm Cortex-A53, 2 Arm Cortex-A53, 4 Arm Cortex-A53 Arm MHz (Max.) 1400 Co-processor(s) 1 Arm Cortex-M4F CPU 64-bit Display type MIPI DPI, OLDI Protocols Ethernet, TSN Ethernet MAC 2-Port 10/100/1000 Hardware accelerators PRU-SS Features Vision Analytics Operating system Linux Security Secure boot Rating Catalog Operating temperature range (C) -40 to 105, 0 to 95
FCCSP (ALW) 425

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm® Cortex®-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device and Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 200-MHz pixel clock support with Independent PLL for each display
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500 Mpixels/sec
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL 3.x/2.0/1.1 + Extensions, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device and Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
    • Max addressable range
      • 8GBytes with DDR4
      • 4GBytes with LPDDR4

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TUV SUD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TUV SUD planned
  • AEC-Q100 qualified

Security:

  • Hardware Security Module
    • Dedicated dual-core Arm Cortex-M4F Security co-processor with 426KB RAM for key and security management, with dedicated device level interconnect for security
    • Dedicated security DMA and IPC subsystem for isolated processing
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 Bits key sizes
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-Fly encryption support for OSPI interface in XIP mode

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit running up to 333 MHz and Industrial Communication Subystem (PRU-ICSS)
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU with SECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory with SECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of 30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection
    • Trace over USB supported

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with 166-MHz DDR / 200-MHz SDR
    • Support for Serial NAND and Serial NOR flash devices
    • Up to 4 CS supported
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm technology
  • 13 mm x 13 mm, 0.5-mm pitch, 425-pin FCCSP BGA (ALW)
  • 17.2 mm x 17.2 mm, 0.8-mm pitch, 441-pin FCBGA (AMC)

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4 GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 Core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm® Cortex®-M4F MCU at up to 400 MHz
    • 256KB SRAM with SECDED ECC
  • Dedicated Device and Power Manager

Multimedia:

  • Display subsystem
    • Dual display support
    • 1920x1080 @ 60fps for each display
    • 1x 2048x1080 + 1x 1280x720
    • Up to 200-MHz pixel clock support with Independent PLL for each display
    • OLDI/LVDS (4 lanes - 2x) and 24-bit RGB parallel interface
    • Support safety feature such as freeze frame detection and MISR data check
  • 3D Graphics Processing Unit
    • 1 pixel per clock or higher
    • Fillrate greater than 500 Mpixels/sec
    • >500 MTexels/s, >8 GFLOPs
    • Supports at least 2 composition layers
    • Supports up to 2048x1080 @60fps
    • Supports ARGB32, RGB565 and YUV formats
    • 2D graphics capable
    • OpenGL 3.x/2.0/1.1 + Extensions, Vulkan 1.2
  • One Camera Serial interface (CSI-Rx) - 4 Lane with DPHY
    • MIPI CSI 1.3 Compliant + MIPI-DPHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA

Memory Subsystem:

  • Up to 816KB of On-chip RAM
    • 64KB of On-chip RAM (OCSRAM) with SECDED ECC , Can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 256KB of On-chip RAM with SECDED ECC in Cortex-M4F MCU subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device and Power Manager Subsystem
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4, DDR4 memory types
    • 16-Bit data bus with inline ECC
    • Supports speeds up to 1600 MT/s
    • Max addressable range
      • 8GBytes with DDR4
      • 4GBytes with LPDDR4

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TUV SUD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TUV SUD planned
  • AEC-Q100 qualified

Security:

  • Hardware Security Module
    • Dedicated dual-core Arm Cortex-M4F Security co-processor with 426KB RAM for key and security management, with dedicated device level interconnect for security
    • Dedicated security DMA and IPC subsystem for isolated processing
  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
    • Supports cryptographic cores
      • AES – 128/192/256 Bits key sizes
      • SHA2 – 224/256/384/512
      • DRBG with true random number generator
      • PKA (Public Key Accelerator) to Assist in RSA/ECC processing
    • DMA support
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
  • Secure storage support
  • On-the-Fly encryption support for OSPI interface in XIP mode

PRU Subsystem:

  • Dual-core Programmable Real-Time Unit running up to 333 MHz and Industrial Communication Subystem (PRU-ICSS)
  • Intended for driving GPIO for cycle accurate protocols such as additional:
    • General Purpose Input/Output (GPIO)
    • UARTs
    • I2C
    • External ADC
  • 16KByte program memory per PRU with SECDED ECC
  • 8KB data memory per PRU with SECDED ECC
  • 32KB general purpose memory with SECDED ECC
  • CRC32/16 HW accelerator
  • Scratch PAD memory with 3 banks of 30 x 32-bit registers
  • 1 Industrial 64-bit timer with 9 capture and 16 compare events, along with slow and fast compensation
  • 1 interrupt controller (INTC), minimum of 64 input events supported

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time sensitive networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection
    • Trace over USB supported

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50 MHz
    • Up to 16/10/6 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Secure Digital (SD) (4b+4b+8b) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0 and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133 MHz
    • Flexible 8- and 16-Bit Asynchronous Memory Interface With up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH Code to Support 4-, 8-, or 16-Bit ECC
    • Uses Hamming Code to Support 1-Bit ECC
    • Error Locator Module (ELM)
      • Used With the GPMC to Locate Addresses of Data Errors From Syndrome Polynomials Generated Using a BCH Algorithm
      • Supports 4-, 8-, and 16-Bit Per 512-Byte Block Error Location Based on BCH Algorithms
  • OSPI/QSPI with 166-MHz DDR / 200-MHz SDR
    • Support for Serial NAND and Serial NOR flash devices
    • Up to 4 CS supported
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low power modes supported by Device Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Optimal Power Management Solution:

  • Recommended TPS65219 Power Management ICs (PMIC)
    • Companion PMIC specially designed to meet device power supply requirements
    • Flexible mapping and factory programmed configurations to support different use cases

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm technology
  • 13 mm x 13 mm, 0.5-mm pitch, 425-pin FCCSP BGA (ALW)
  • 17.2 mm x 17.2 mm, 0.8-mm pitch, 441-pin FCBGA (AMC)

The low-cost AM62x Sitara™ MPU family of application processors are built for Linux® application development. With scalable Arm® Cortex®-A53 performance and embedded features, such as: dual-display support and 3D graphics acceleration, along with an extensive set of peripherals that make the AM62x device well-suited for a broad range of industrial and automotive applications while offering intelligent features and optimized power architecture as well.

Some of these applications include:

  • Industrial HMI
  • EV charging stations
  • Touchless building access
  • Driver monitoring systems

AM62x Sitara™ processors are industrial-grade in the 13 x 13 mm package (ALW) and can meet the AEC-Q100 automotive standard in the 17.2 x 17.2 mm package (AMC). Industrial and Automotive functional safety requirements can be addressed using the integrated Cortex-M4F cores and dedicated peripherals, which can all be isolated from the rest of the AM62x processor.

The 2-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM62x enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM62x device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications

Products in the AM62x processor family:

  • AM623—IoT and gateway SoC with Arm® Cortex®-A53 based object and gesture recognition
  • AM625—Human-Machine InteractionSoC with Arm® Cortex®-A53 based edge AI, full-HD dual-display

The low-cost AM62x Sitara™ MPU family of application processors are built for Linux® application development. With scalable Arm® Cortex®-A53 performance and embedded features, such as: dual-display support and 3D graphics acceleration, along with an extensive set of peripherals that make the AM62x device well-suited for a broad range of industrial and automotive applications while offering intelligent features and optimized power architecture as well.

Some of these applications include:

  • Industrial HMI
  • EV charging stations
  • Touchless building access
  • Driver monitoring systems

AM62x Sitara™ processors are industrial-grade in the 13 x 13 mm package (ALW) and can meet the AEC-Q100 automotive standard in the 17.2 x 17.2 mm package (AMC). Industrial and Automotive functional safety requirements can be addressed using the integrated Cortex-M4F cores and dedicated peripherals, which can all be isolated from the rest of the AM62x processor.

The 2-port Gigabit Ethernet switch has one internal port and two external ports with Time-Sensitive Networking (TSN) support. An additional PRU module on the device enables real-time I/O capability for customer’s own use cases. In addition, the extensive set of peripherals included in AM62x enables system-level connectivity, such as: USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. The AM62x device also supports secure boot for IP protection with the built-in Hardware Security Module (HSM) and employs advanced power management support for portable and power-sensitive applications

Products in the AM62x processor family:

  • AM623—IoT and gateway SoC with Arm® Cortex®-A53 based object and gesture recognition
  • AM625—Human-Machine InteractionSoC with Arm® Cortex®-A53 based edge AI, full-HD dual-display

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詳細

  • 他のリファレンス・デザインと入門用アプリケーション・ソフトウェアを表示するには AM62x Development Portal (英語) にアクセスしてください。
  • SysConfig DDR サブシステムのレジスタ構成ツールについては、DDR Subsystem Register (英語) にアクセスしてください。
  • 対話型で直観的なグラフィカル・ツールを使用して、デバイス・ピン・マルチプレックスに関連する初期化コードの有効化、構成、生成を行う方法については、SysConfig PINMUX Tool (英語) にアクセスしてください。

技術資料

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種類 タイトル 最新の英語版をダウンロード 日付
* データシート AM62x Sitara™ Processors データシート PDF | HTML 2022年 6月 1日
* エラッタ AM62x Sitara Errata (Rev. A) PDF | HTML 2022年 7月 19日
* ユーザー・ガイド AM62x Sitara Processors Technical Reference Manual 2022年 8月 4日
アプリケーション・ノート PRU-ICSS Feature Comparison (Rev. F) PDF | HTML 2022年 8月 5日
アプリケーション・ノート Sitara™ AM62x Benchmarks PDF | HTML 2022年 7月 27日
技術記事 Top 3 design considerations for EV charging 2022年 6月 20日
アプリケーション・ノート Powering the AM62x with the TPS65219 PMIC (Rev. A) PDF | HTML 2022年 6月 9日
技術記事 3 key considerations for the next generation of HMI 2022年 6月 1日
ホワイト・ペーパー AM62x 採用で、低消費電力の組込みシステムを実現可能 PDF | HTML 2022年 5月 31日
アプリケーション・ノート AM62x Power Consumption Summary PDF | HTML 2022年 5月 30日
アプリケーション・ノート Sitara Processor Power Distribution Networks: Implementation and Analysis (Rev. E) PDF | HTML 2022年 5月 25日
アプリケーション・ノート AM62x Extended Power-On Hours PDF | HTML 2022年 5月 13日
アプリケーション・ノート High-Speed Interface Layout Guidelines (Rev. I) PDF | HTML 2022年 4月 14日
アプリケーション・ノート AM62x DDR Board Design and Layout Guidelines 2022年 3月 9日
アプリケーション・ノート AM62x Schematic Review Checklist PDF | HTML 2022年 2月 9日
アプリケーション・ノート AM62x PCB Escape Routing PDF | HTML 2021年 12月 10日
技術記事 Difficult to see. Always in motion is the future 2016年 1月 4日
技術記事 Announcing the new entry-level Sitara processor 2015年 12月 9日

設計および開発

追加の事項や他のリソースを参照するには、以下のタイトルをクリックすると、詳細ページを表示できます。

評価ボード

SK-AM62 — Sitara™ AM62x プロセッサ向け AM62x スタータ・キット評価基板 (EVM)

AM62x スタータ・キット評価基板 (EVM) は、AM62x SoC (システム・オン・チップ) をベースとしたスタンドアロンのテスト / 開発プラットフォームです。AM62x プロセッサは、クワッドコアの 64 ビット Arm Cortex A53 マイクロプロセッサ、シングルコアの Arm Cortex-R5F マイコン (MCU)、および Arm Cortex-M4F マイコンで構成されています。

SK-AM62 を使用すると、ドット密度 (DPI) の高い HDMI (高品位マルチメディア・インターフェイス) や LVDS (...)

TI.com で取り扱いなし
ソフトウェア開発キット (SDK)

MCU-PLUS-SDK-AM62X MCU+ SDK for AM62x – RTOS, No-RTOS

The AM62x processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which (...)

サポートされている製品とハードウェア

サポートされている製品とハードウェア

製品
Arm ベースのプロセッサ
AM623 Arm® Cortex®-A53 ベースの物体検出機能とジェスチャ認識機能搭載、IoT (モノのインターネット) とゲートウェイ向け SoC AM625 Arm® Cortex®-A53 ベースのエッジ側 AI とフル HD デュアル・ディスプレイを組み合わせた、人間と機械の対話型操作向け SoC
ハードウェア開発
評価ボード
SK-AM62 Sitara™ AM62x プロセッサ向け AM62x スタータ・キット評価基板 (EVM)
クラウドで評価することができます ダウンロードオプション
ソフトウェア開発キット (SDK)

PROCESSOR-SDK-LINUX-RT-AM62X Processor SDK RT-Linux for AM62x

The AM62x processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which (...)

サポートされている製品とハードウェア

サポートされている製品とハードウェア

製品
Arm ベースのプロセッサ
AM623 Arm® Cortex®-A53 ベースの物体検出機能とジェスチャ認識機能搭載、IoT (モノのインターネット) とゲートウェイ向け SoC AM625 Arm® Cortex®-A53 ベースのエッジ側 AI とフル HD デュアル・ディスプレイを組み合わせた、人間と機械の対話型操作向け SoC
ハードウェア開発
評価ボード
SK-AM62 Sitara™ AM62x プロセッサ向け AM62x スタータ・キット評価基板 (EVM)
ダウンロードオプション
ソフトウェア開発キット (SDK)

PROCESSOR-SDK-LINUX-AM62X Processor SDK Linux for AM62X

The AM62x processor Linux®, Android™ and TI MCU+ software development kits (SDKs) are unified software platforms for embedded processors providing easy setup and fast out-of-box access to benchmarks and demonstrations.

All releases of this SDK are consistent across TI's broad portfolio for which (...)

サポートされている製品とハードウェア

サポートされている製品とハードウェア

製品
Arm ベースのプロセッサ
AM623 Arm® Cortex®-A53 ベースの物体検出機能とジェスチャ認識機能搭載、IoT (モノのインターネット) とゲートウェイ向け SoC AM625 Arm® Cortex®-A53 ベースのエッジ側 AI とフル HD デュアル・ディスプレイを組み合わせた、人間と機械の対話型操作向け SoC
ハードウェア開発
評価ボード
SK-AM62 Sitara™ AM62x プロセッサ向け AM62x スタータ・キット評価基板 (EVM)
ダウンロードオプション
アプリケーション・ソフトウェアとフレームワーク

FNDRS-3P-LINUX — Secure, customizable, Linux platform for building scalable IoT and Edge devices

Foundries.io provides a secure, customizable, Linux platform for building scalable IoT and Edge devices.

FoundriesFactory is a cloud service, enabling product developers to develop, deploy and maintain Linux software, applications and services for IoT and Edge devices and fleets, over product (...)

サンプル・コードまたはデモ

ASTC-3P-VLAB-EVM-SIM — ASTC VLAB virtual development platforms and tools

VLAB Works is the industry leader in software technology for modeling, simulation, and virtual prototyping of embedded electronic systems. VLAB technologies and solutions enable the application of automation and agile processes to embedded systems development. VLAB Works helps customers design (...)
From: VLAB Works
サポート・ソフトウェア

MCW-3P-FACEREC — MulticoreWare software for face recognition, authentication and human behavior analytics

MulticoreWare is a software engineering product and services company that combines its expertise in artificial intelligence and embedded systems to create Linux-based solutions to solve real world challenges in imaging, building automation, retail, authentication, smart city and a variety of (...)
From: Multicoreware Inc.
サポート・ソフトウェア

PLMR-3P-PEODET — Plumerai people detection - accurate and efficient AI model

Plumerai makes deep learning tiny and radically more efficient to enable inference at reduced compute needs on low cost and low-power consumption hardware. Plumerai focuses on full stack, and has offices in London, Amsterdam and Warsaw.

Plumerai has developed a complete software solution for (...)

From: Plumerai Ltd
シミュレーション・モデル

AM62x IBIS-AMI Model AM62x IBIS-AMI Model

シミュレーション・モデル

AM62x IBIS Model AM62x IBIS Model

シミュレーション・モデル

AM62x BSDL Model AM62x BSDL Model

シミュレーション・モデル

AM62x Thermal Model AM62x Thermal Model

計算ツール

AM62X-PET-CALC AM62x 電力推定ツール (PET:Power Estimation Tool)

AM62x 電力推定ツール (PET) スプレッドシートを使用すると、測定済みデータとシミュレーション・データに基づいて、消費電力の推定値を計算できます。推定値は現状のまま提供されるもので、特定の精度を保証するものではありません。消費電力は、電気的パラメータ、シリコン・プロセスのばらつき、環境条件、動作中にプロセッサが実行する使用事例によって異なります。

実際の消費電力は、実際のシステムを使用して確認する必要があります。このツールは、現実的な動作モードの消費電力を推定することを意図しており、電源のサイズ設定を目的としたものではありません。

(...)

アセンブリの図面

SK-AM62-P1 Design File Package SK-AM62-P1 Design File Package

パッケージ ピン数 ダウンロード
FCCSP (ALW) 425 オプションの表示

購入と品質

記載されている情報:
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL rating / リフローピーク温度
  • MTBF/FIT 推定値
  • 原材料組成
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果

推奨製品には、この TI 製品に関連するパラメータ、評価基板、またはリファレンス・デザインが存在する可能性があります。

サポートとトレーニング

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ビデオ