The controller initiates a data transfer by generating a start condition. The start condition is when a high-to-low transition occurs on the SDA line while SCL is high, as shown in #T4908770-78. All I²C-compatible devices should recognize a start condition.

Figure 8-6 START and STOP Condition

The controller then generates the SCL pulses, and transmits the 8-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the controller ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see #T4908770-79). All devices recognize the address sent by the controller and compare it to their internal fixed addresses. Only the peripheral device with a matching address generates an acknowledge (see #T4908770-80) by pulling the SDA line low during the entire high period of the ninth SCL cycle. Upon detecting this acknowledge, the controller knows that communication link with a peripheral has been established.

Figure 8-7 Bit Transfer on the Serial Interface

The controller generates further SCL cycles to either transmit data to the peripheral (R/W bit 0) or receive data from the peripheral (R/W bit 1). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an acknowledge signal can either be generated by the controller or by the peripheral, depending on which one is the receiver. The 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as necessary. To signal the end of the data transfer, the controller generates a stop condition by pulling the SDA line from low to high while the SCL line is high (see #T4908770-78). This releases the bus and stops the communication link with the addressed peripheral. All I²C compatible devices must recognize the stop condition. Upon receipt of a stop condition, all devices know that the bus is released, and wait for a start condition followed by a matching address. If a transaction is terminated prematurely, the controller needs to send a STOP condition to prevent the peripheral I²C logic from remaining in an incorrect state. Attempting to read data from register addresses not listed in this section results in FFh being read out.