The DAC38RF82 (or DAC38RF89) has eight configurable JESD204B serial lanes. The highest speed of each SerDes lane is 12.5 Gbps. Because the primary operating frequency of the SerDes is determined by its reference clock and PLL multiplication factor, there is a limit on the lowest SerDes rate supported. To support lower speed application, each receiver should be configured to operate at half, quarter or eighth of the full rate via field RATE in register SRDS_CFG2 (8.5.87). Refer to Table 2 for details.
|00||Full rate. Four data samples taken per SerDes PLL output clock cycle.|
|01||Half rate. Two data samples taken per SerDes PLL output clock cycle.|
|10||Quarter rate. One data samples taken per SerDes PLL output clock cycle.|
|11||Eighth rate. One data samples taken every two SerDes PLL output clock cycles.|