The JESD204B standard for Device Subclass 1 introduces a SYSREF signal that can be used as a global timing reference to align the phase of the internal local multiframe clock (LMFC) and frame clock across multiple devices. This allows the system to achieve deterministic latency and align data samples across several data converters. The SYSREF signal accomplishes this goal by identifying a device clock edge for each chip that can be used as an alignment reference. In particular, the LMFC and frame clock align to the device clock edge upon which the SYSREF transition from “0” to “1” is sampled. SYSREF may be periodic, one-shot, or “gapped” periodic and its period must be a multiple of the LMFC period.
With high-speed device clocks, the phase of the SYSREF signals relative to the device clock must meet the setup/hold time requirements of each individual device clock. Historically, this has been done by controlling the board-level routing delay and/or employing commercial clock distribution capable of generating device clocks and SYSREF signals with programmable delays and with the option of splitting SYSREF into multiple SYSREFS, each with its own fine-tuned delay. Since the DAC38RF82 (or DAC38RF89) supports device clock frequencies up to 9 GHz, a SYSREF capture circuit is includes in the DAC38RF82 (or DAC38RF89) that allows a relaxation in meeting the device clock setup and hold.
The SYSREF capture circuit provides:
The concepts behind the SYSREF capture scheme are illustrated in Figure 31.
To understand Figure 31, to begin with we’ll ignore the SYSREF phase tolerance windows in the lower portion of the figure and focus on the blue clock waveform at the top of the figure. This waveform represents the device clock input to a particular DAC chip. The green arrows, labeled “R” and “F”, correspond to the rising and falling edges of this clock (ignoring for the moment the additional arrows labeled “ER” and "EF”). While previous devices with lower device clocks captured SYSREF only on the rising edge of the device clock, the new scheme samples SYSREF on the falling edge as well, which provides more flexibility when optimizing the setup and hold time of the SYSREF capture path. Moreover, each time a rising SYSREF edge is captured, the chip remembers the clock phase during which the event occurred, and the system designer can later read back the phase information to observe the SYSREF timing relative to the device clock at the internal capture point. If SYSREF transitions close to the rising or falling clock edge sampling points the capture flop setup and hold time may not be met and the observed phase may be unreliable and subject to meta-stability phenomenon.
To reduce the sensitivity to setup/hold/meta-stability concerns an “early” version of the device clock is generated within the DAC and additional SYSREF samples are taken at the “early falling” and “early rising” edges of the clock (labeled “EF” and “ER”, respectively, in Figure 31). The resulting set of four samples is used to narrow down the timing of the rising SYSREF edge to one of four possible clock phases. If the rising SYSREF transition takes place between the “EF” and “F” samples, then SYSREF is said to occur in phase θ1. Similarly, if it takes place between the “F” and “ER” samples, then it is said to occur in phase θ2. If SYSREF transitions between the “ER” and “R” samples, then it is said to occur in phase θ3. And, finally, if the SYSREF rising edge event happens between the “R” and “EF” samples, then it is said to occur in phase θ4. As mentioned before, the chip remembers all observed SYSREF phases and the user can later read them back. Since the delay between “early” and “on time” versions of the clock is intentionally chosen to be larger than the setup/hold/meta-stability window, at most one of the four samples can be affected even when the SYSREF transitions right at one of the four sampling points. Thus, the uncertainty in the observed SYSREF timing is limited to adjacent phases, and with twice as many sampling phases the resolution of the timing information is improved by a factor of two.
Referring to the lower portion of Figure 31, the user can now see how this information regarding the observed SYSREF phases is used to devise a reliable SYSREF capture methodology with a high degree of tolerance to manufacturing and environmental variations in SYSREF phase. Based on the SYSREF phases observed for a particular DAC chip during system characterization, the system designer can select one of four so-called “phase tolerance window” options (denoted “’00”, “01”, “10”, and “11”) to maximize immunity to manufacturing and environmental variations. For example, consider the default phase tolerance window labeled “window=00” in the figure. If, during characterization, the system designer observes (by reading back the recorded phase observations) that the rising SYSREF edge nominally occurs in either θ1 or θ2 or both (i.e. θ12) then he would program that particular DAC chip to use phase tolerance window “00”. This mapping is indicated in the figure with the label “θ1|θ12|θ2: window=00”. Having programmed the device to use window “00”, all future SYSREF events that occur in θ1 or θ2 would trigger the LMFC and frame clock to be aligned using the following rising clock edge as the alignment reference (as indicated by the red arrow pointing to rising clock edge “R” and labeled “Window=00/01 alignment edge”).
The full extent of each phase tolerance window is indicated in the figure using “box and whisker” plots. For the “window=00” example, the “box” portion of the plot indicates that the phase tolerance window is centered on θ12 (to be precise on the boundary between θ1 and θ2) and the “whisker” portion indicates that even if the rising edge of SYSREF occurs as early as the preceding θ4 or as late as the following θ3 it still results in LMFC and frame clock alignment to the same rising clock edge indicated by the red arrow labeled “Window=00/01 alignment edge”. When programmed for phase tolerance window “00”, the DAC chip is tolerant to variations in the SYSREF timing ranging from a rising SYSREF edge that occurs just after one rising edge of clock to just before the next rising edge of the clock. The qualifying phrases “just after” and “just before” are used here to indicate that the SYSREF transition must occur far enough away from the rising edges of the clock to avoid setup/hold violations and prevent the device from concluding that the SYSREF transition has crossed out off the phase tolerance window when in fact it has not. The tolerance range for window “00” is from rising clock edge to rising clock edge and is indicated in the figure by the green text labeled “tolerance = R↔R”.
Following the above example, if characterization reveals SYSREF timing centered on θ23 then phase tolerance window “01” (with tolerance for SYSREF rising edge events from EF to EF) should be chosen. Notice that this option is tolerant even to rising SYSREF edges that occur after the rising device clock edge (i.e. in θ4) and will treat them just as if they had occurred in one of the earlier three phases, aligning to the same rising device clock edge indicated by the red arrow labeled “Window=00/01 Alignment Edge”. This allows the system designer to tolerate PCB design errors and/or environmental and manufacturing variations – achieving his intended alignment without having to make physical changes to the board to adjust the SYSREF timing.
Similarly, if characterization indicates that SYSREF timing is centered on θ34 or θ41 then phase tolerance window “10” or “11” can be selected, resulting in tolerance for “F↔F” or “ER↔ER” SYSREF timing, respectively. Note, however, that in these two cases the alignment reference edge is by default taken to be the subsequent rising edge of the device clock. Since this may not be the desired behavior, the DAC38RF82 (or DAC38RF89) allows the user to program in an optional alignment offset of θ1 if the default offset of 0 does not achieve the desired alignment. This feature is illustrated in Figure 32 where the user can see that by setting the alignment offset to -1, phase tolerance windows “10” and “11” can be made to trigger alignment to the earlier rising device clock edge used by windows “00” and “01”. Alternatively, the window “00” and “01” alignment edge can be pushed one cycle later by setting their alignment offset to +1.
Several important controls related to SYSREF alignment and capture timing are contained in register SYSR_CAPTURE (8.5.78). For example, as mentioned before, the device is capable of monitoring the observed phases of the rising SYSREF edge events; however, in order to avoid unwanted noise coupling from the SYSREF circuits into the DAC output, the SYSREF monitoring circuits are disabled by default. Field SYSR_STATUS_ENA enables SYSREF status monitoring. Field SYSR_PHASE_WDW contains the the phase tolerance window selected for normal operation, which is optimized during characterization. Field SYSR_ALIGN_DLY contains the control that allows the system designer to optionally offset the SYSREF alignment event by ±1 device clock cycles. Field SYSR_STATUS_ENA enables the SYSREF capture alignment accumulation and will generate alarms when enabled. Writing a “1” to field SYSR_ALIGN_SYNC clears the accumulated SYSREF alignment statistics. The SYSREF alignment block can be bypassed completely by field SYSREF_BYPASS_ALIGN, in which case SYSREF is latched by the rising edge of DACCLK.
When field SYSR_STATUS_ENA is high the device records the phase associated with each SYSREF event for use in characterizing the SYSREF capture timing and selecting an appropriate phase tolerance window. The phase data is available in two forms. First, each of the four phases has a corresponding “sticky” alarm flag indicating which phases have been observed since the last time the register was cleared. In addition, the device also accumulates statistics on the relative number of occurrences of each phase spanning multiple SYSREF events using saturating 8-bit counters. These accumulated real-time SYSREF statistics allow us to account for time-varying effects during characterization such as potential timing differences between the 1st and Nth edges in a “gapped” SYSREF pulse train. The counters are fields PHASE1_CNT and PHASE2_CNT in register SYSREF12_CNT (8.5.10), PHASE3_CNT and PHASE4_CNT in register SYSREF34_CNT (8.5.11), and ALIGN_TO_R1_CNT and ALIGN_TO_R3_CNT in register SYSREF_ALIGN_R (8.5.9).
The accumulated SYSREF statistics can be cleared by writing ‘1’ to SYSR_ALIGN_SYNC. This sync signal affects only the SYSREF statistics monitors and does not cause a sync of any other portions of the design. Before collecting phase statistics, the user must first enable the SYSREF status monitoring logic by setting the SYSR_STATUS_ENA bit. The user must then generate a repeating SYSREF input before using SYSR_ALIGN_SYNC to clear the statistic counters. This is necessary to flush invalid data out of the status pipeline.
The “sticky” alarm flags indicating which of the four phases have been observed since the last SYSR_ALIGN_SYNC write of ‘1’ are fields ALM_SYSRPHASE1 to ALM_SYSRPHASE4 and are contained in the ALM_SYSREF_DET register (8.5.6).