The DAC38RF82 (or DAC38RF89) JESD204B interface has two differential SYNC outputs called SYNC0 and SYNC1 to support one or two links. Alternatively, GPO0 and GPO1 can be used to output SYNC as a single-ended CMOS level. Each of the differential or CMOS outputs is enabled by a 2-bit register (fields GPO0_SEL, GPO1_SEL, SYNC0B_SEL, SYNC1B_SEL in register IO_CONFIG 8.5.2), with bit 0 enabling multi-DUC1 SYNC and bit 1 enabling multi-DUC2 SYNC. If both are enabled, the SYNC\ signals are OR’ed.
The SYNC signal can be asserted low by the receiver either to make a synchronization request to initialize/reinitialize the link or to report an error to the transmitter. Synchronization requests must have a minimum duration of five frames plus nine octets rounded up to the nearest whole number of frames. To report an error, the SYNC signal is asserted for exactly two frames. The transmitter interprets any negative edge of its SYNC input as an error and any SYNC assertion lasting four frames or longer as a synchronization request. See the following sections in the standard for more details.