|LEGEND: R/W = Read/Write; R = Read only; -n = value after reset|
|14:12||CDRVSER_SYSREF_DLY||R/W||000||Programmable delay the SYSREF by N dacclk cycles to the CDRV_SER clock dividers. By offsetting the clock to the different multi-DUC blocks, clock mixing could potentially be reduced.|
|11:7||Not used||R/W||00000||Not used|
|6:4||SYSREF_MODE||R/W||001||Determines how SYSREF is used to sync the clock dividers in the CDRV_SER block.
000 = Don’t use SYSREF pulse
001 = Use all SYSREF pulses
010 = Use only the next SYSREF pulse
011 = Skip one SYSREF pulse then use only the next one
100 = Skip one SYSREF pulse then use all pulses.
|3:2||SYSREF_DLY||R/W||00||Delays the SYSREF into the CDRV_SER capture FF through 1 of 4 choices. This allows for extra delay in case the timing of the clock or SYSREF path isn’t as good as we think.|