The DAC38RF82 (or DAC38RF89) has a programmable output clock on CLKTX+/- balls that is a divided version of the internal DAC sample clock, either with or without PLL. Two frequency dividers, either DACCLK/3 or DACCLK/4, are available by programming field CLK_TX_DIV4 in register CLK_OUT (8.5.71). The output swing voltage is programmable from approximately 125 to 1460 mVPP-DIFF through field CLK_TX_SWING in register CLK_OUT (8.5.71).
Field CLK_TX_IDLE in register CLK_OUT (8.5.71) enables an idle state, in which the pins are driven to the proper common-mode levels in order to charge the external AC coupling caps but the clock output is disabled. The output clock circuit can be put to sleep by field CLK_TX_SLEEP in register SLEEP_CONFIG (8.5.70).