JAJSLB2D november 2014 – april 2023 DLP9500UV
PRODUCTION DATA
PIN (1) | TYPE (I/O/P) | SIGNAL | DATA RATE (2) | INTERNAL TERM (3) | CLOCK | DESCRIPTION | TRACE (MILS) | |
---|---|---|---|---|---|---|---|---|
NAME | NO. | |||||||
DATA BUS A | ||||||||
D_AN(0) | F2 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | Input data bus A (2x LVDS) | 512.01 |
D_AN(1) | H8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 158.79 | |
D_AN(2) | E5 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 471.24 | |
D_AN(3) | G9 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 159.33 | |
D_AN(4) | D2 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 585.41 | |
D_AN(5) | G3 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 551.17 | |
D_AN(6) | E11 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 229.41 | |
D_AN(7) | F8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 300.54 | |
D_AN(8) | C9 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 346.35 | |
D_AN(9) | H2 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 782.27 | |
D_AN(10) | B10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 451.52 | |
D_AN(11) | G15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 74.39 | |
D_AN(12) | D14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 194.26 | |
D_AN(13) | F14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 148.29 | |
D_AN(14) | C17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 244.9 | |
D_AN(15) | H16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 73.39 | |
D_AP(0) | F4 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 509.63 | |
D_AP(1) | H10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 152.59 | |
D_AP(2) | E3 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 464.09 | |
D_AP(3) | G11 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 152.39 | |
D_AP(4) | D4 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 591.39 | |
D_AP(5) | G5 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 532.16 | |
D_AP(6) | E9 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 230.78 | |
D_AP(7) | F10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 300.61 | |
D_AP(8) | C11 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 338.16 | |
D_AP(9) | H4 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 773.17 | |
D_AP(10) | B8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 449.57 | |
D_AP(11) | H14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | Input data bus A (2x LVDS) |
71.7 |
D_AP(12) | D16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 198.69 | |
D_AP(13) | F16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 143.72 | |
D_AP(14) | C15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 240.14 | |
D_AP(15) | G17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 74.05 | |
DATA BUS B | ||||||||
D_BN(0) | AH2 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | Input data bus B (2x LVDS) | 525.25 |
D_BN(1) | AD8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 190.59 | |
D_BN(2) | AJ5 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 525.25 | |
D_BN(3) | AE3 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 494.91 | |
D_BN(4) | AG9 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 222.67 | |
D_BN(5) | AE11 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 205.45 | |
D_BN(6) | AH10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 309.05 | |
D_BN(7) | AF10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 285.62 | |
D_BN(8) | AK8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 483.58 | |
D_BN(9) | AG5 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 711.58 | |
D_BN(10) | AL11 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 462.21 | |
D_BN(11) | AE15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 74.39 | |
D_BN(12) | AH14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 194.26 | |
D_BN(13) | AF14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 156 | |
D_BN(14) | AJ17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 247.9 | |
D_BN(15) | AD16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 111.52 | |
D_BP(0) | AH4 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 525.02 | |
D_BP(1) | AD10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 190.61 | |
D_BP(2) | AJ3 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 524.22 | |
D_BP(3) | AE5 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 476.07 | |
D_BP(4) | AG11 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 222.8 | |
D_BP(5) | AE9 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 219.48 | |
D_BP(6) | AH8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 306.55 | |
D_BP(7) | AF8 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 298.04 | |
D_BP(8) | AK10 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 480.31 | |
D_BP(9) | AG3 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | Input data bus B (2x LVDS) |
727.18 |
D_BP(10) | AL9 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 461.02 | |
D_BP(11) | AD14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 71.35 | |
D_BP(12) | AH16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 197.69 | |
D_BP(13) | AF16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 150.38 | |
D_BP(14) | AJ15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 243.14 | |
D_BP(15) | AE17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 113.36 | |
DATA BUS C | ||||||||
D_CN(0) | B14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | Input data bus C (2x LVDS) | 459.04 |
D_CN(1) | E15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 342.79 | |
D_CN(2) | A17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 456.22 | |
D_CN(3) | G21 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 68.24 | |
D_CN(4) | B20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 362.61 | |
D_CN(5) | F20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 163.07 | |
D_CN(6) | D22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 204.16 | |
D_CN(7) | G23 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 105.59 | |
D_CN(8) | B26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 450.51 | |
D_CN(9) | F28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 302.04 | |
D_CN(10) | C29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 429.8 | |
D_CN(11) | G27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 317.1 | |
D_CN(12) | D26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 276.76 | |
D_CN(13) | H28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 186.78 | |
D_CN(14) | E29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 311.3 | |
D_CN(15) | J29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 262.62 | |
D_CP(0) | B16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 463.64 | |
D_CP(1) | E17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 347.65 | |
D_CP(2) | A15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 456.45 | |
D_CP(3) | H20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 67.72 | |
D_CP(4) | B22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 362.76 | |
D_CP(5) | F22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 161.69 | |
D_CP(6) | D20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | Input data bus C (2x LVDS) | 195.09 |
D_CP(7) | H22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 104.86 | |
D_CP(8) | B28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 451.41 | |
D_CP(9) | F26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 294.22 | |
D_CP(10) | C27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 429.68 | |
D_CP(11) | G29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 314.98 | |
D_CP(12) | D28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 276.04 | |
D_CP(13) | H26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 186.25 | |
D_CP(14) | E27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 312.07 | |
D_CP(15) | J27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 262.94 | |
DATA BUS D | ||||||||
D_DN(0) | AK14 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | Input data bus D (2x LVDS) | 492.53 |
D_DN(1) | AG15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 342.78 | |
D_DN(2) | AL17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 491.83 | |
D_DN(3) | AE21 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 74.24 | |
D_DN(4) | AK20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 356.23 | |
D_DN(5) | AF20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 163.07 | |
D_DN(6) | AH22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 204.16 | |
D_DN(7) | AE23 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 105.59 | |
D_DN(8) | AK26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 450.51 | |
D_DN(9) | AF28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 302.04 | |
D_DN(10) | AJ29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 429.8 | |
D_DN(11) | AE27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 298.87 | |
D_DN(12) | AH26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | Input data bus D (2x LVDS) | 276.76 |
D_DN(13) | AD28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 186.78 | |
D_DN(14) | AG29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 311.3 | |
D_DN(15) | AC29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 262.62 | |
D_DP(0) | AK16 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 495.13 | |
D_DP(1) | AG17 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 342.47 | |
D_DP(2) | AL15 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 492.06 | |
D_DP(3) | AD20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 67.72 | |
D_DP(4) | AK22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 356.37 | |
D_DP(5) | AF22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 161.98 | |
D_DP(6) | AH20 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 195.09 | |
D_DP(7) | AD22 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 102.86 | |
D_DP(8) | AK28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 451.41 | |
D_DP(9) | AF26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 296.7 | |
D_DP(10) | AJ27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 429.68 | |
D_DP(11) | AE29 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 302.74 | |
D_DP(12) | AH28 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 276.04 | |
D_DP(13) | AD26 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 186.25 | |
D_DP(14) | AG27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 312.07 | |
D_DP(15) | AC27 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 262.94 | |
DATA CLOCKS | ||||||||
DCLK_AN | D10 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | Input data bus A Clock (2x LVDS) | 325.8 |
DCLK_AP | D8 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | 319.9 | |
DCLK_BN | AJ11 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | Input data bus B Clock (2x LVDS) | 318.92 |
DCLK_BP | AJ9 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | 318.74 | |
DCLK_CN | C23 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | Input data bus C Clock (2x LVDS) | 252.01 |
DCLK_CP | C21 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | 241.18 | |
DCLK_DN | AJ23 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | Input data bus D Clock (2x LVDS) | 252.01 |
DCLK_DP | AJ21 | Input | LVCMOS | — | Differentially terminated – 100 Ω | — | 241.18 | |
DATA CONTROL INPUTS | ||||||||
SCTRL_AN | J3 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | Serial control for data bus A (2x LVDS) | 608.14 |
SCTRL_AP | J5 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_A | 607.45 | |
SCTRL_BN | AF4 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | Serial control for data bus B (2x LVDS) | 698.12 |
SCTRL_BP | AF2 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_B | 703.8 | |
SCTRL_CN | E23 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | Serial control for data bus C (2x LVDS) | 232.46 |
SCTRL_CP | E21 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_C | 235.21 | |
SCTRL_DN | AG23 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | Serial control for data bus D (2x LVDS) | 235.53 |
SCTRL_DP | AG21 | Input | LVCMOS | DDR | Differentially terminated – 100 Ω | DCLK_D | 235.66 | |
SERIAL COMMUNICATION AND CONFIGURATION | ||||||||
SCPCLK | AE1 | Input | LVCMOS | — | pull-down | — | Serial port clock | 324.26 |
SCPDO | AC3 | Output | LVCMOS | — | — | SCP_CLK | Serial port output | 281.38 |
SCPDI | AD2 | Input | LVCMOS | — | pull-down | SCP_CLK | Serial port input | 261.55 |
SCPEN | AD4 | Input | LVCMOS | — | pull-down | SCP_CLK | Serial port enable | 184.86 |
PWRDN | B4 | Input | LVCMOS | — | pull-down | — | Device reset | 458.78 |
MODE_A | J1 | Input | LVCMOS | — | pull-down | — | Data bandwidth mode select | 471.57 |
MODE_B | G1 | Input | LVCMOS | — | pull-down | — | 521.99 | |
MICROMIRROR CLOCKING PULSE (BIAS RESET) | ||||||||
MBRST(0) | L5 | Input | Analog | — | — | — | Micromirror clocking pulse reset MBRST signals clock micromirrors into state of LVCMOS memory cell associated with each mirror. | 898.97 |
MBRST(1) | M28 | Input | Analog | — | — | — | 621.98 | |
MBRST(2) | P4 | Input | Analog | — | — | — | 846.88 | |
MBRST(3) | P30 | Input | Analog | — | — | — | 784.18 | |
MBRST(4) | L3 | Input | Analog | — | — | — | 763.34 | |
MBRST(5) | P28 | Input | Analog | — | — | — | 749.61 | |
MBRST(6) | P2 | Input | Analog | — | — | — | 878.25 | |
MBRST(7) | T28 | Input | Analog | — | — | — | 783.83 | |
MBRST(8) | M4 | Input | Analog | — | — | — | 969.36 | |
MBRST(9) | L29 | Input | Analog | — | — | — | 621.24 | |
MBRST(10) | T4 | Input | Analog | — | — | — | 918.43 | |
MBRST(11) | N29 | Input | Analog | — | — | — | 685.14 | |
MBRST(12) | N3 | Input | Analog | — | — | — | 812.31 | |
MBRST(13) | L27 | Input | Analog | — | — | — | 591.89 | |
MBRST(14) | R3 | Input | Analog | — | — | — | 878.5 | |
MBRST(15) | V28 | Input | Analog | — | — | — | 660.15 | |
MBRST(16) | V4 | Input | Analog | — | — | — | 848.64 | |
MBRST(17) | R29 | Input | Analog | — | — | — | 796.31 | |
MBRST(18) | Y4 | Input | Analog | — | — | — | 715 | |
MBRST(19) | AA27 | Input | Analog | — | — | — | 604.35 | |
MBRST(20) | W3 | Input | Analog | — | — | — | 832.39 | |
MBRST(21) | W27 | Input | Analog | — | — | — | 675.21 | |
MBRST(22) | AA3 | Input | Analog | — | — | — | 861.18 | |
MBRST(23) | W29 | Input | Analog | — | — | — | 662.66 | |
MBRST(24) | U5 | Input | Analog | — | — | — | 850.06 | |
MBRST(25) | U29 | Input | Analog | — | — | — | 726.56 | |
MBRST(26) | Y2 | Input | Analog | — | — | — | 861.48 | |
MBRST(27) | AA29 | Input | Analog | — | — | — | 683.83 | |
MBRST(28) | U3 | Input | Analog | — | — | — | 878.5 | |
MBRST(29) | Y30 | Input | Analog | — | — | — | 789.2 | |
POWER | ||||||||
VCC | A3, A5, A7, A9, A11, A13, A21, A23, A25, A27, A29, B2, | Power | Analog | — | — | — | Power for LVCMOS logic | — |
C1, C31, E31, G31, J31, K2, L31, N31, R31, U31, W31, | ||||||||
AA31, AC1, AC31, AE31, AG1, AG31, AJ31, AK2, | ||||||||
AK30, AL3, AL5, AL7, AL19, AL21, AL23, AL25, AL27 | ||||||||
VCCI | H6, H12, H18, H24, M6, M26, P6, P26, T6, T26, V6, V26, | Power | Analog | — | — | — | Power supply for LVDS Interface | — |
Y6, Y26, AD6, AD12, AD18, AD24 | ||||||||
VCC2 | L1, N1, R1, U1, W1, AA1 | Power | Analog | — | — | — | Power for high voltage CMOS logic | — |
VSS | A1, B12, B18, B24, B30, C7, C13, C19, C25, D6, D12, | Power | Analog | — | — | — | Common return for all power inputs | — |
D18, D24, D30, E1, E7, E13, E19, E25, F6, F12, F18, F24, | ||||||||
F30, G7, G13, G19, G25, K4, K6, K26, K28, K30, M2, M30, | ||||||||
N5, N27, R5, T2, T30, U27, V2, V30, W5, Y28, AB2, AB4, | ||||||||
AB6, AB26, AB28, AB30, AD30, AE7, AE13, AE19, | ||||||||
AE25, AF6, AF12, AF18, AF24, AF30, AG7, AG13, | ||||||||
AG19, AG25, AH6, AH12, AH18, AH24, AH30, AJ1, | ||||||||
AJ7, AJ13, AJ19, AJ25, AK6, AK12, AK18, AL29 | ||||||||
RESERVED SIGNALS (NOT FOR USE IN SYSTEM) | ||||||||
RESERVED_FC | J7 | Input | LVCMOS | — | pull-down | — | Pins should be connected to VSS | — |
RESERVED_FD | J9 | Input | LVCMOS | — | pull-down | — | — | |
RESERVED_PFE | J11 | Input | LVCMOS | — | pull-down | — | — | |
RESERVED_STM | AC7 | Input | LVCMOS | — | pull-down | — | — | |
RESERVED_AE | C3 | Input | LVCMOS | — | pull-down | — | — | |
NO_CONNECT | A19, B6, C5, H30, J13, J15, J17, J19, J21, J23, J25, R27, | — | — | — | — | — | No connection (any connection to these terminals may result in undesirable effects) | — |
AA5, AC11, AC13, AC15, AC17, AC19, AC21, AC23, | ||||||||
AC25, AC5, AC9, AK24, AK4, AL13 |