over operating free-air temperature range (unless otherwise noted)(1) | MIN | NOM | MAX | UNIT |
---|
ELECTRICAL (2) (3) |
VCC | Supply voltage for LVCMOS core logic | 3.0 | 3.3 | 3.6 | V |
VCC1 | Supply voltage for LVDS receivers | 3.0 | 3.3 | 3.6 | V |
VCC2 | Mirror electrode and HVCMOS supply voltage | 8.25 | 8.5 | 8.75 | V |
VMBRST | Clocking Pulse Waveform Voltage applied to MBRST[29:0] Input Pins (supplied by DLPA200s) | -27 | | 26.5 | V |
|VCCI–VCC| | Supply voltage delta (absolute value) (4) | | | 0.3 | V |
ENVIRONMENTAL (5) For Illumination Source Between 420 nm and 700 nm |
TARRAY | Array temperature, Long–term operational (12)(7) (6)(8) | 20 | 25-45 | 65 (13) | | °C |
Array temperature, Short–term operational (12)(7) (9) | 0 | | 20 |
TWINDOW | Window temperature test points TP2 and TP3, Long-term operational(8). | 10 | | 70 | °C |
|TDELTA| | Absolute temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1.(11) | | | 10 | °C |
ILLVIS | Illumination(10) | | | Thermally limited | W/cm2 |
ENVIRONMENTAL (5) For Illumination Source Between 400 nm and 420 nm |
TARRAY | Array temperature, Long–term operational (12)(7) (6)(8) | 20 | | 30 | °C |
TWINDOW | Window temperature test points TP2 and TP3, Long-term operational(8) | | | 30 | °C |
|TDELTA| | Absolute temperature delta between the window test points (TP2, TP3) and the ceramic test point TP1.(11) | | | 10 | °C |
ILL | Illumination(10) | | | 11 | W/cm2 |
| | 26.6 | W |
ENVIRONMENTAL (5) For Illumination Source <400 nm and >700 nm |
TARRAY | Array temperature, Long–term operational (12)(7)
(6)(8) | 20 | | 40 (13) | °C |
Array temperature, Short–term operational (12)(7)
(9) | 0 | | 20 |
TWINDOW | Window temperature test points TP2 and TP3, Long-term operational(8) | 10 | | 70 | °C |
ILL | Illumination(10) | | | 10 | mW/cm2 |
(1) The functional performance of the device specified in this
data sheet is achieved when operating the device within the limits defined by
the Recommended Operating Conditions. No level of performance is implied
when operating the device above or below the Recommended Operating
Conditions limits.
(2) Voltages VCC, VCC1, and VCC2
are required for proper DMD operation. VSS must also be
connected.
(3) All voltages are referenced to common ground
VSS.
(4) Exceeding the recommended allowable absolute voltage difference
between VCC and VCC1 may result in excess current draw.
The difference between VCC and VCC1, |VCC –
VCC1|, should be less than the specified limit.
(5) Optimal, long-term performance and optical efficiency of the
Digital Micromirror Device (DMD) can be affected by various application
parameters, including illumination spectrum, illumination power density,
micromirror landed duty-cycle, ambient temperature (storage and operating), DMD
temperature, ambient humidity (storage and operating), and power on or off duty
cycle. TI recommends that application-specific effects be considered as early as
possible in the design cycle.
(6) Simultaneous exposure of the DMD to the maximum
Recommended Operating Conditions for temperature and UV
illumination will reduce device lifetime.
(8) Long-term is defined as the usable life of the device.
(9) Array temperatures beyond those specified as long-term are
recommended for short-term conditions only (power-up). Short-term is defined as
cumulative time over the usable life of the device and is less than 500
hours.
(10) Total integrated illumination power density on the array in the
indicated wavelength range.
(11) The temperature delta is the highest difference between the
ceramic test point (TP1) and window test points (TP2) and (TP3) in
Figure 8-11.
(13) Per
Figure 7-1, the maximum operational array temperature should be derated based on the
micromirror landed duty cycle that the DMD experiences in the end application.
Refer to
Section 8.7 for a definition of micromirror landed duty cycle.