JAJSDA0 June   2017 DRV10983-Q1

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Description (Continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Regulators
        1. 8.3.1.1 Step-Down Regulator
        2. 8.3.1.2 3.3-V and 1.8-V LDO
      2. 8.3.2 Protection Circuits
        1. 8.3.2.1 Thermal Shutdown
        2. 8.3.2.2 UVLO
        3. 8.3.2.3 Current Protection
        4. 8.3.2.4 Lock
      3. 8.3.3 Motor Speed Control
      4. 8.3.4 Load Dump Handling
      5. 8.3.5 Sleep or Standby Condition
      6. 8.3.6 EEPROM Access
    4. 8.4 Device Functional Modes
      1. 8.4.1  Motor Parameters
        1. 8.4.1.1 Motor Resistance
        2. 8.4.1.2 Motor Velocity Constant
      2. 8.4.2  Starting the Motor Under Different Initial Conditions
        1. 8.4.2.1 Case 1 - Motor is Stationary
        2. 8.4.2.2 Case 2 - Motor is Spinning in the Forward Direction
        3. 8.4.2.3 Case 3 - Motor is Spinning in the Reverse Direction
      3. 8.4.3  Motor Start Sequence
        1. 8.4.3.1 Initial Speed Detect
        2. 8.4.3.2 Motor Resynchronization
        3. 8.4.3.3 Reverse Drive
        4. 8.4.3.4 Motor Brake
        5. 8.4.3.5 Motor Initialization
          1. 8.4.3.5.1 Align
          2. 8.4.3.5.2 IPD
            1. 8.4.3.5.2.1 IPD Operation
            2. 8.4.3.5.2.2 IPD Release Mode
            3. 8.4.3.5.2.3 IPD Advance Angle
          3. 8.4.3.5.3 Motor Start
        6. 8.4.3.6 Start-Up Timing
      4. 8.4.4  Align Current
      5. 8.4.5  Start-Up Current Setting
        1. 8.4.5.1 Start-Up Current Ramp-Up
      6. 8.4.6  Closed Loop
        1. 8.4.6.1 Half-Cycle Control and Full-Cycle Control
        2. 8.4.6.2 Analog-Mode Speed Control
        3. 8.4.6.3 Digital PWM-Input-Mode Speed Control
        4. 8.4.6.4 I2C-Mode Speed Control
        5. 8.4.6.5 Closed-Loop Accelerate
        6. 8.4.6.6 Control Coefficient
        7. 8.4.6.7 Commutation Control Advance Angle
      7. 8.4.7  Current Limit
        1. 8.4.7.1 Acceleration Current Limit
      8. 8.4.8  Lock Detect and Fault Handling
        1. 8.4.8.1 Lock0: Lock-Detection Current Limit Triggered
        2. 8.4.8.2 Lock1: Abnormal Speed
        3. 8.4.8.3 Lock2: Abnormal Kt
        4. 8.4.8.4 Lock3 (Fault3): No-Motor Fault
        5. 8.4.8.5 Lock4: Open-Loop Motor-Stuck Lock
        6. 8.4.8.6 Lock5: Closed Loop Motor Stuck Lock
      9. 8.4.9  Anti Voltage Supression Function
        1. 8.4.9.1 Mechanical AVS Function
        2. 8.4.9.2 Inductive AVS Function
      10. 8.4.10 PWM Output
      11. 8.4.11 FG Customized Configuration
        1. 8.4.11.1 FG Output Frequency
        2. 8.4.11.2 FG Open Loop and Lock Behavior
      12. 8.4.12 Diagnostics and Visibility
        1. 8.4.12.1 Motor-Status Readback
        2. 8.4.12.2 Motor-Speed Readback
        3. 8.4.12.3 Motor Electrical-Period Readback
        4. 8.4.12.4 Motor Velocity Constant Read Back
        5. 8.4.12.5 Motor Estimated Position by IPD
        6. 8.4.12.6 Supply-Voltage Readback
        7. 8.4.12.7 Speed-Command Readback
        8. 8.4.12.8 Speed-Command Buffer Readback
        9. 8.4.12.9 Fault Diagnostics
    5. 8.5 Register Maps
      1. 8.5.1 I2C Serial Interface
      2. 8.5.2 Register Map
      3. 8.5.3 Register Descriptions
        1. 8.5.3.1  FaultReg Register (address = 0x00) [reset = 0x00]
        2. 8.5.3.2  MotorSpeed Register (address = 0x01) [reset = 0x00]
        3. 8.5.3.3  MotorPeriod Register (address = 0x02) [reset = 0x00]
        4. 8.5.3.4  MotorKt Register (address = 0x03) [reset = 0x00]
        5. 8.5.3.5  MotorCurrent Register (address = 0x04) [reset = 0x00]
        6. 8.5.3.6  IPDPosition-SupplyVoltage Register (address = 0x05) [reset = 0x00]
        7. 8.5.3.7  SpeedCmd-spdCmdBuffer Register (address = 0x06) [reset = 0x00]
        8. 8.5.3.8  AnalogInLvl Register (address = 0x07) [reset = 0x00]
        9. 8.5.3.9  DeviceID-RevisionID Register (address = 0x08) [reset = 0x00]
        10. 8.5.3.10 DeviceID-RevisionID Register (address = 0x08) [reset = 0x00]
        11. 8.5.3.11 Unused Registers (addresses = 0x011 Through 0x2F)
        12. 8.5.3.12 SpeedCtrl Register (address = 0x30) [reset = 0x00]
        13. 8.5.3.13 EEPROM Programming1 Register (address = 0x31) [reset = 0x00]
        14. 8.5.3.14 EEPROM Programming2 Register (address = 0x32) [reset = 0x00]
        15. 8.5.3.15 EEPROM Programming3 Register (address = 0x33) [reset = 0x00]
        16. 8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00]
        17. 8.5.3.17 EEPROM Programming5 Register (address = 0xYY) [reset = 0x00]
        18. 8.5.3.18 EEPROM Programming6 Register (address = 0x36) [reset = 0x00]
        19. 8.5.3.19 Unused Registers (addresses = 0x37 Through 0x5F)
        20. 8.5.3.20 EECTRL Register (address = 0x60) [reset = 0x00]
        21. 8.5.3.21 Unused Registers (addresses = 0x61 Through 0x8F)
        22. 8.5.3.22 CONFIG1 Register (address = 0x90) [reset = 0x00]
        23. 8.5.3.23 CONFIG2 Register (address = 0x91) [reset = 0x00]
        24. 8.5.3.24 CONFIG3 Register (address = 0x92) [reset = 0x00]
        25. 8.5.3.25 CONFIG4 Register (address = 0x93) [reset = 0x00]
        26. 8.5.3.26 CONFIG5 Register (address = 0x94) [reset = 0x00]
        27. 8.5.3.27 CONFIG6 Register (address = 0x95) [reset = 0x00]
        28. 8.5.3.28 CONFIG7 Register (address = 0x96) [reset = 0x00]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 商標
    2. 12.2 静電気放電に関する注意事項
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7 Specifications

7.1 Absolute Maximum Ratings

over operating ambient temperature range (1)
MIN MAX UNIT
Input voltage(2) VCC –0.3 28 V
VCC during load dump (VCC slew rate < 1 V/µs) –0.3 45
SPEED –0.3 4
PGND, SWGND –0.3 0.3
SCL, SDA –0.3 4
DIR –0.3 4
Output voltage (2) U, V, W –1 30 V
SW –1 30
VREG –0.3 7
FG –0.3 4
VCP –0.3 VCC + 6
CPN –0.3 30
CPP –0.3 VCC + 6
V3P3 –0.3 4
V1P8 –0.3 2.5
TJ_MAX Maximum junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the ground terminal (GND) unless otherwise noted.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per AEC Q100-002, all pins (1) ±2000 V
Charged device model (CDM), per AEC Q100-011, all pins ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage VCC, register contents preserved 4.5 12 45 V
VCC, motor operational 6.2 12 28
Voltage range U, V, W –0.7 29 V
SCL, SDA, FG, SPEED, DIR –0.1 3.3 3.6
PGND, GND, SWGND –0.1 0.1
VCP, CPP –0.1 VCC + 5
CPN –0.1 VCC
SW –0.7 VCC
Current range Step-down regulator output current (buck mode) 100 mA
Step-down regulator output current (resistive mode) 5
V3P3 LDO output current (no load on VREG and V3P3 in resitive mode) 5
TA Operating ambient temperature –40 125 °C

7.4 Thermal Information

THERMAL METRIC (1) DRV10983-Q1 UNIT
PWP (HTSSOP)
24 PINS
RθJA Junction-to-ambient thermal resistance 36.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 17.4 °C/W
RθJB Junction-to-board thermal resistance 14.8 °C/W
ψJT Junction-to-top characterization parameter 0.4 °C/W
ψJB Junction-to-board characterization parameter 14.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W
(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics.

7.5 Electrical Characteristics

over operating voltage and ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT (DRV10983Q)
IVccSLEEP1 Sleep current VSPEED = 0 V; VCC = 12 V; TA = 25℃ 48 54 µA
VSPEED = 0 V; VCC = 12 V; across temperature 81
IVcc Active current VSPEED > 0 V; buck regulator with inductor; no motor load 10 15 mA
VSPEED > 0 V; buck regulator with resistor; no motor load 13 16
SUPPLY CURRENT (DRV10983SQ)
IVccSTBY Standby current VSPEED = 0 V; buck regulator with
inductor		 8.5 14 mA
VSPEED = 0 V; buck regulator with
resistor		 11 15
IVcc Active current VSPEED > 0 V; buck regulator with
inductor; no motor load		 10 15 mA
VSPEED > 0 V; buck regulator with
resistor; no motor load		 13 16
UVLO
VUVLO_R UVLO rising threshold voltage 5.8 6 6.2 V
VUVLO_F UVLO falling threshold voltage 5.6 5.8 6 V
VUVLO_HYS UVLO threshold voltage hysteresis 170 195 220 mV
VV1P8_UVLO_R V1P8 UVLO rising threshold 1.5 1.6 1.7 V
VV1P8_UVLO_F V1P8 UVLO falling threshold 1.4 1.55 1.65 V
VV3P3_UVLO_R V3P3 UVLO rising threshold 2.7 2.85 2.95 V
VV3P3_UVLO_F V3P3 UVLO falling threshold 2.5 2.7 2.8 V
VVREG_UVLO_R VREG UVLO rising threshold 4 4.2 4.3 V
VVREG_UVLO_F VREG UVLO falling threshold 3.9 4.2 V
LDO OUTPUT
V3P3 Output voltage Buck regulator with inductor, 20-mA load 3.1 3.3 3.5 V
Buck regulator with resistor, no load
IV3P3_MAX Maximum load from V3P3 Only with inductor mode of buck operation, with resistor mode no load 20 mA
V1P8 Output voltage No load 1.7 1.8 1.9 V
STEP-DOWN REGULATOR
VREG Regulator output voltage LSW = 47 µH, CSW = 10 µF
Iload = 100 mA		 4.5 5 5.5 V
RSW = 39 Ω, CSW = 10 µF
Iload = 5 mA
IREG_MAX_L Maximum load from VREG in switching mode LSW = 47 µH, CSW = 10 µF 100 mA
IREG_MAX_R Maximum load from VREG in linear mode RSW = 39 Ω, CSW = 10 µF 5 mA
INTEGRATED MOSFET
rDS(ON) Series resistance (H + L) TA = 25˚C; V(VCC) > 6.5 V; Io = 1 A 250 400 mΩ
TA = 125˚C; V(VCC) > 6.5V; Io = 1 A 325 550
SPEED – ANALOG MODE
VAN/A_FS Analog full-speed voltage V(V3P3) × 0.9 V(V3P3) V
VAN/A_ZS Analog zero-speed voltage 0 100 mV
tSAM Sampling period for analog voltage on SPEED pin  320 µs
VAN/A_RES Analog voltage resolution 6.5 mV
SPEED – PWM DIGITAL MODE
VDIG_IH PWM input high voltage 2.2 V
VDIG_IL PWM input low voltage 0.6 V
ƒPWM PWM input frequency 0.1 100 kHz
SLEEP/STANDBY CONDITION
VEN_SL_SB Analog voltage to enter sleep/standby SpdCtrlMd = 0 (analog mode) 100 mV
VEX_SL Analog voltage to exit sleep SpdCtrlMd = 0 (analog mode) 2.2 V
VEX_SB Analog voltage to exit standby SpdCtrlMd = 0 (analog mode) 0.17 3.3 V
tEX_SL Time to exit from sleep mode SpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SL 		2 µs
tEX_SB Time to exit from standby mode SpdCtrlMd = 0 (analog mode)
VSPEED > VEX_SB 		700 800 ms
tEX_SL_SB Time to exit from sleep or standby condition SpdCtrlMd = 1 (PWM mode)
VSPEED > VDIG_IH 		2 µs
tEN_SL_SB Time to enter sleep or standby condition SpdCtrlMd = 1 (PMW mode)
VSPEED < VDIG_IL 		60 ms
DIGITAL I/O (DIR INPUT, FG OUTPUT )
VDIR_H Input high 2.2 V
VDIR_L Input low 0.6 V
VFG_OH Output high voltage Io = 5 mA 3.3 V
VFG_OL Output low voltage Io = 5 mA 0.6 V
I2C SERIAL INTERFACE
VI2C_H Input high 2.2 V
VI2C_L Input low 0.6 V
fI2C I2C clock frequency 0 400 kHz
LOCK DETECTION RELEASE TIME
tLOCK_OFF Lock release time 5 s
tLCK_ETR Lock enter time 0.3 s
OVERCURRENT PROTECTION
IOC_limit_HS HS overcurrent protection VCC < 28.5 V 3.5 4.25 5.5 A
IOC_limit_LS LS overcurrent protection VCC < 28.5 V 3.5 4.25 5.5 A
THERMAL SHUTDOWN
TSDN Junction temperature shutdown threshold 150 165 180 °C
TSDN_HYS Junction temperature shutdown hysteresis 15 20 25 °C
TWARN Junction temperature warning threshold 115 125 140 °C
PHASE DRIVER
SLPH_LH0 Phase slew rate switching low to high PHslew = 0; measure 20% to 80%;
VCC = 12 V		 85 120 145 V/µs
SLPH_LH1 Phase slew rate switching low to high PHslew = 1; measure 20% to 80%;
VCC = 12 V		 60 80 100 V/µs
SLPH_LH2 Phase slew rate switching low to high PHslew = 2; measure 20% to 80%;
VCC = 12 V		 38 50 62 V/µs
SLPH_LH3 Phase slew rate switching low to high PHslew = 3; measure 20% to 80%;
VCC = 12 V		 27 35 44 V/µs
SLPH_HL0 Phase slew rate switching high to low PHslew = 0; measure 80% to 20%;
VCC = 12 V		 85 120 145 V/µs
SLPH_HL1 Phase slew rate switching high to low PHslew = 1; measure 80% to 20%;
VCC = 12 V		 59 80 100 V/µs
SLPH_HL2 Phase slew rate switching high to low PHslew = 2; measure 80% to 20%;
VCC = 12 V		 36 50 60 V/µs
SLPH_HL3 Phase slew rate switching high to low PHslew = 3; measure 80% to 20%;
VCC = 12 V		 25 35 45 V/µs
LOAD DUMP PROTECTION
VOV_R Load dump protection mode entry on rising VCC threshold 28.5 29.2 30 V
VOV_F Load dump protection mode exit on falling VCC threshold 27.7 28.2 28.8 V
VOV_HYS Load dump protection mode hysteresis 0.73 1 1.1 V

7.6 Typical Characteristics

DRV10983-Q1 D001.gif
Figure 1. Supply Current vs Power Supply Voltage
DRV10983-Q1 D002.gif
Figure 2. Switching Regulator Output vs Power Supply Voltage