8.3.1.1 Step-Down Regulator

The DRV10983-Q1 device includes a step-down hysteretic voltage regulator that can operate with either an external inductor or with an external resistor. The best efficiency is achieved when an external inductor (see Figure 3) is used. The regulator output voltage is 5 V. When the regulated voltage drops by the hysteresis level, the high-side FET turns on to raise the regulated voltage back to the target of 5 V. The switching frequency of the hysteretic regulator is not constant and changes with load.

If the step-down regulator is configured with an external inductor, it can deliver current to the load as specified by I_{REG_MAX_L}. If the step-down regulator is configured with an external resistor it, can deliver current to the load as specified by I_{REG_MAX_R}.

Buck Regulator with External Inductor

Buck Regulator with External Resistor

Figure 3. Step-Down Regulator Configurations

8.3.1.2 3.3-V and 1.8-V LDO

The DRV10983-Q1 device includes a 3.3-V LDO and a 1.8-V LDO. The 1.8-V LDO is for internal circuits only. The 3.3-V LDO is mainly for internal circuits, but can also drive external loads not to exceed I_{V3P3_MAX}. For example, it can work as a pullup voltage for the FG, DIR, SDA, and SCL interface.

Both the V1P8 and V3P3 capacitors must be connected to GND.

8.3.2.1 Thermal Shutdown

The DRV10983-Q1 device has a built-in thermal shutdown function, which shuts down the device when the junction temperature is more than T_SDN˚C and recovers operating conditions when the junction temperature falls to T_SDN – T_{SDN_HYS}˚C.

The OverTemp status bit (address 0x00, bit 15) is set during thermal shutdown. In addition to the thermal shutdown function there is a warning bit that is set whenever the device exceeds T_WARN and is indicated by the TempWarning bit of the FaultReg register (address 0x00, bit 14).

8.3.2.2 UVLO

The DRV10983-Q1 device has a built-in UVLO function block. The device is locked out when V_CC is below V_{UVLO_F} and is unlocked when V_CC is above V_{UVLO_R}. The hysteresis of the UVLO threshold is V_{UVLO_HYS}. In addition to the main supply, the step-down regulator, charge pump, and 3.3-V LDO all have undervoltage lockout monitors.

8.3.2.3 Current Protection

The overcurrent shutdown function acts to protect the device if the current, as measured from the FETs, exceeds the I_OC-limit threshold. It protects the device in the event of a short-circuit condition on the motor phases. This includes phase shorts to GND, phase shorts to phase, or phase shorts to V_CC. The DRV10983-Q1 device places the output drivers into a high-impedance state until the lock time t_{LOCK_OFF} has expired. The OverCurr status bit of the FaultReg register (address 0x00, bit 11) is set.

The DRV10983-Q1 device also provides acceleration current-limit and lock-detection current-limit functions to protect the device and motor (see Current Limit and Lock Detect and Fault Handling ).

8.3.2.4 Lock

When the motor is blocked or stopped by an external force, lock protection is triggered, and the device stops driving the motor immediately. After the lock release time t_{LOCK_OFF}, the DRV10983-Q1 device resumes driving the motor again. If the lock condition is still present, it enters the next lock protection cycle, and repeats until the lock condition is removed. With this lock protection, the motor and device do not overheat or become damaged due to the motor being locked (see Lock Detect and Fault Handling ).

During a lock condition the Status register indicates which of the locks has occurred.

Table 1. Conditions to Enter or Exit Sleep or Standby Condition

Table 2. Minimum PWM Duty Cycle Requirement for Different PWM Frequency to Exit Sleep Condition

8.4.1.1 Motor Resistance

For a wye-connected motor, the motor phase resistance refers to the resistance from the phase output to the center tap, R_{PH_CT} (denoted as R_{PH_CT} in Figure 9).

Figure 9. Wye-Connected Motor Resistance

For a delta-connected motor, the motor phase resistance refers to the equivalent phase to center tap in the wye configuration. In Figure 10, it is denoted as R_Y. R_{PH_CT} = R_Y.

For both the delta-connected motor and the wye-connected motor, the easy way to get the equivalent R_{PH_CT} is to measure the resistance between two phase terminals (R_{PH_PH}), and then divide this value by two, R_{PH_CT} = ½ R_{PH_PH}.

Figure 10. Delta-Connected Motor and the Equivalent Wye Connections

The motor resistance (R_{PH_CT}) must be converted to a 7-bit digital register value Rm[6:0] to program the motor resistance value. The digital register value can be determined as follows:

1. Convert the motor resistance (R_{PH_CT}) to a digital value where the LSB is weighted to represent 9.67 mΩ: Rmdig = R_{PH_CT} / 0.00967.
2. Encode the digital value such that Rmdig = RMValue[3:0] << RMShift[2:0].

The maximum resistor value, R_{PH_CT}, that can be programmed for the DRV10983-Q1 device is 18.5 Ω, which represents Rmdig = 1920 and an encoded Rm[6:0] value of 0x7Fh. The minimum resistor the DRV10983-Q1 device supports is 0.029 Ω, R_{PH_CT}, which represents Rmdig = 3.

For convenience, the encoded value for Rm[6:0] can also be obtained from Table 3.

8.4.1.2 Motor Velocity Constant

The motor velocity constant, Kt[6:0] describes the phase-to-phase BEMF voltage of the motor as a function of the motor velocity.

Figure 11 shows the measurement technique for this constant as used in the DRV10983-Q1 device.

Figure 11. Kt_PH Definition

With the motor coasting, use an oscilloscope to capture the differential voltage waveform between any two phases. Derive the motor velocity constant used by the DRV10983-Q1 device as shown in Equation 1.

The measured motor velocity constant (Kt_PH) must be converted to a 7-bit digital register value Kt[6:0] (combination of KtShift[2:0] and KtValue[3:0]) to program the motor velocity constant value. The digital register value can be determined as follows:

1. Convert the measured Kt_PH to a weighted digital value: Kt_{ph_dig} = 1090 × Kt_PH
2. Encode the digital value such that Kt_{ph_dig} = KtValue[3:0] << KtShift[2:0].

The maximum Kt_PH that can be programmed is 1760 mV/Hz. This represents a digital value of 1920 and an encoded Kt[6:0] value of 0x7Fh. The minimum Kt_PH that can be programmed is 0.92 mV/Hz, which represents a digital value of 1 and an encoded Kt[6:0] value of 0x01h.

For convenience, the encoded value of Kt[6:0] may also be obtained from Table 4.

8.4.2.1 Case 1 – Motor is Stationary

If the motor is stationary, the commutation logic must be initialized to be in phase with the position of the motor. The DRV10983-Q1 device provides for two options to initialize the commutation logic to the motor position. Initial position detect (IPD) determines the position of the motor based on the deterministic inductance variation, which is often present in BLDC motors. The align-and-go technique forces the motor into alignment by applying a voltage across a particular motor phase to force the motor to rotate in alignment with this phase.

8.4.2.2 Case 2 – Motor is Spinning in the Forward Direction

If the motor is spinning forward with enough velocity, the DRV10983-Q1 device may be configured to go directly into closed loop. By resynchronizing to the spinning motor, the user achieves the fastest possible start-up time for this initial condition.

8.4.2.3 Case 3 – Motor is Spinning in the Reverse Direction

If the motor is spinning in the reverse direction, the DRV10983-Q1 device provides several methods to convert it back to the forward direction.

One method, reverse drive, allows the motor to be driven so that it accelerates through zero velocity. The motor achieves the shortest possible spin-up time in systems where the motor is spinning in the reverse direction.

If this feature is not selected, then the DRV10983-Q1 device may be configured either to wait for the motor to stop spinning or to brake the motor. After the motor has stopped spinning, the motor start-up sequence proceeds as it would for a motor which is stationary.

Take care when using the reverse-drive or brake feature to ensure that the current is limited to an acceptable level and that the supply voltage does not surge as a result of energy being returned to the power supply.

Figure 12. Start the Motor Under Different Initial Conditions

8.4.3.1 Initial Speed Detect

The ISD function is used to identify the initial condition of the motor. If the function is disabled, the DRV10983-Q1 device does not perform the initial speed detect function and treats the motor as if it is stationary.

Phase-to-phase comparators are used to detect the zero crossings of the motor’s BEMF voltage while it is coasting (motor phase outputs are in the high-impedance state). Figure 14 shows the configuration of the comparators.

Figure 14. Initial Speed Detect Function

If the UW comparator output is lagging the UV comparator by 60°, the motor is spinning forward. If the UW comparator output is leading the UV comparator by 60°, the motor is spinning in reverse.

The motor speed is determined by measuring the time between two rising edges of either of the comparators.

If neither of the comparator outputs toggles for a given amount of time, the condition is defined as stationary. The amount of time can be programmed by setting the register bits ISDThr[1:0].

8.4.3.2 Motor Resynchronization

The resynchronize function works when the ISD function is enabled and determines that the initial state of the motor is spinning in the forward direction. The speed and position information measured during ISD are used to initialize the drive state of the DRV10983-Q1 device, which can transition directly into the closed-loop running state without needing to stop the motor.

8.4.3.3 Reverse Drive

The ISD function measures the initial speed and the initial position; the DRV10983-Q1 reverse drive function acts to reverse accelerate the motor through zero speed and to continue accelerating until the closed loop threshold is reached (see Figure 15). If the reverse speed is greater than the threshold configured in RvsDrThr[1:0], then the DRV10983-Q1 device waits until the motor coasts to a speed that is less than the threshold before driving the motor to reverse accelerate.

Figure 15. Reverse Drive Function

Reverse drive is suitable for applications where the load condition is light at low speed and relatively constant and where the reverse speed is low (that is, a fan motor with little friction). For other load conditions, the motor brake function provides a method for helping force a motor which is spinning in the reverse direction to stop spinning before a normal start-up sequence.

8.4.3.4 Motor Brake

The motor brake function can be used to stop the spinning motor before attempting to start the motor. The brake is applied by turning on all three of the low-side driver FETs.

Brake is enabled by configuring a non-zero BrkDoneThr[2:0]. Brake is applied for a time configured by BrkDoneThr[2:0] (forward or reverse). After the motor is stopped, the motor position is unknown. To proceed with restarting in the correct direction, the IPD or align-and-go algorithm must be implemented. The motor start sequence is the same as it would be for a motor starting in the stationary condition.

The motor brake function can be disabled. The motor skips the brake state and attempts to spin the motor as if it were stationary. If this happens while the motor is spinning in either direction, the start-up sequence may not be successful.

8.4.3.5 Motor Initialization

8.4.3.5.2 IPD

The inductive sense method is used to determine the initial position of the motor when IPD is enabled. IPD is enabled by selecting IPDCurrThr[3:0] to any value other than 0000.

IPD can be used in applications where reverse rotation of the motor is unacceptable. Because IPD is not required to wait for the motor to align with the commutation, it can allow for a faster motor start sequence. IPD works well when the inductance of the motor varies as a function of position. Because it works by pulsing current to the motor, it can generate acoustics which must be taken into account when determining the best start method for a particular application.

8.4.3.5.2.1 IPD Operation

The IPD operates by sequentially applying voltage across two of the three motor phases according to the following sequence: VW WV UV VU WU UW (see Figure 16). When the current reaches the threshold configured in IPDCurrThr[3:0], the voltage across the motor is stopped. The DRV10983-Q1 device measures the time it takes from when the voltage is applied until the current threshold is reached. The time varies as a function of the inductance in the motor windings. The state with the shortest time represents the state with the minimum inductance. The minimum inductance is because of the alignment of the north pole of the motor with this particular driving state.

Figure 16. IPD Function

8.4.3.5.2.2 IPD Release Mode

Two options are available for stopping the voltage applied to the motor when the current threshold is reached. If IPDRlsMd = 0, the recirculate mode is selected. The low-side (S6) MOSFET remains on to allow the current to recirculate between the MOSFET (S6) and body diode (S2) (see Figure 17). If IPDRlsMd = 1, the tri-state mode is selected. Both the high-side (S1) and low-side (S6) MOSFETs are turned off and the current flies back across the body diodes into the power supply (see Figure 18).

In the high-impedance state, the phase current has a faster settle-down time, but that could result in a surge on V_CC. Manage this with appropriate selection of either a clamp circuit or by providing sufficient capacitance between V_CC and GND. If the voltage surge cannot be contained and if it is unacceptable for the application, then select the recirculate mode. When selecting the recirculate mode, select the IPDClk[1:0] bits to give the current in the motor windings enough time to decay to 0.

Figure 17. IPD Release Mode 0

Figure 18. IPD Release Mode 1

8.4.3.5.2.3 IPD Advance Angle

After the initial position is detected, the DRV10983-Q1 device begins driving the motor at an angle specified by IPDAdvcAgl[1:0].

Advancing the drive angle anywhere from 0° to 180° results in positive torque. Advancing the drive angle by 90° results in maximum initial torque. Applying maximum initial torque could result in uneven acceleration to the rotor. Select the IPDAdvcAgl[1:0] to allow for smooth acceleration in the application (see Figure 19).

Figure 19. IPD Advance Angle

8.4.3.6 Start-Up Timing

Start-up timing is determined by the align and accelerate time. The align time can be set by AlignTime[2:0]. The accelerate time is defined by the open-to-closed loop threshold Op2ClsThr[4:0] along with the first-order StAccel[2:0](A1) and second-order StAccel2[2:0](A2) accelerate rates. Figure 20 shows the motor start-up process.

Figure 20. Motor Start-Up Process

Select the first-order and second-order accelerate rates to allow the motor to reliably accelerate from zero velocity up to the closed-loop threshold in the shortest time possible. Using a slow accelerate rate during the first order accelerate stage can help improve reliability in applications where it is difficult to accurately initialize the motor with either align or IPD.

Select the open-to-closed loop threshold to allow the motor to accelerate to a speed that generates sufficient BEMF for closed-loop control. This is determined by the velocity constant of the motor based on the relationship described in Equation 2.

8.4.5.1 Start-Up Current Ramp-Up

A fast change in the applied drive current may result in a sudden change in the driving torque. In some applications, this could result in acoustic noise. To avoid this, the DRV10983-Q1 device allows the option of limiting the rate at which the current is applied to the motor. OpLCurrRt[2:0] sets the maximum voltage ramp-up rate that is applied to the motor. The waveforms in Figure 22 show how this feature can be used to gradually ramp the current applied to the motor.

Start driving with fast current ramp	Start driving with slow current ramp

Figure 22. Motor Start-Up Current Ramp

8.4.6.1 Half-Cycle Control and Full-Cycle Control

The estimated BEMF used to control the drive state of the motor has two zero-crosses every electrical cycle. The DRV10983-Q1 device can be configured to update the drive state either once every electrical cycle or twice for every electrical cycle. When AdjMode is programmed to 1, half-cycle adjustment is applied. The control logic is triggered at both the rising edge and falling edge. When AdjMode is programmed to 0, full-cycle adjustment is applied. The control logic is triggered only at the rising edge (see Figure 23).

Half-cycle adjustment provides a faster response when compared with full-cycle adjustment. Use half-cycle adjustment whenever the application requires operation over large dynamic loading conditions. Use the full-cycle adjustment for low-current (<1 A) applications because it offers more tolerance for current-measurement offset errors.

Figure 23. Closed-Loop Control Commutation-Adjustment Mode

8.4.6.2 Analog-Mode Speed Control

The SPEED input pin can be configured to operate as an analog input (SpdCtrlMd = 0).

When configured for analog mode, the voltage range on the SPEED pin can be varied from 0 to V3P3. If
SPEED > V_{ANA_FS}, the speed command is maximum. If V_{ANA_ZS} ≤ SPEED < V_{ANA_FS} the speed command changes linearly according to the magnitude of the voltage applied at the SPEED pin. If SPEED < V_{ANA_ZS} the speed command is to stop the motor. Figure 24 shows the speed command when operating in analog mode.

Figure 24. Analog-Mode Speed Command

8.4.6.3 Digital PWM-Input-Mode Speed Control

If SpdCtrlMd = 1, the SPEED input pin is configured to operate as a PWM-encoded digital input. The PWM duty cycle applied to the SPEED pin can be varied from 0 to 100%. The speed command is proportional to the PWM input duty cycle. The speed command stops the motor when the PWM input keeps at 0 for t_{EN_SL_SB} (see Figure 25).

The frequency of the PWM input signal applied to the SPEED pin is defined as f_PWM. This is the frequency the device can accept to control motor speed. It does not correspond to the PWM output frequency that is applied to the motor phase. The PWM output frequency can be configured to be either 25 kHz when the PWMFreq bit is set to 0 or to 50 kHz when PWMFreq bit is set to 1.

Figure 25. PWM-Mode Speed Command

8.4.6.4 I²C-Mode Speed Control

The DRV10983-Q1 device can also command the speed through the I²C serial interface. To enable this feature, the OverRide bit is set to 1. When the DRV10983-Q1 device is configured to operate in I²C mode, it ignores the signal applied to the SPEED pin.

The speed command can be set by writing the SpdCtrl[8:0] bits. The 9-bit SpdCtrl [8:0] located in the SpeedCtrl registers is used to set the peak amplitude voltage applied to the motor. The maximum speed command is set when SpdCtrl [8:0] is set to 0x1FF (511).

8.4.6.5 Closed-Loop Accelerate

To prevent sudden changes in the torque applied to the motor which could result in acoustic noise, the DRV10983-Q1 device provides the option of limiting the maximum rate at which the speed command changes. ClsLpAccel[2:0] can be programmed to set the maximum rate at which the speed command changes (shown in Figure 26).

Figure 26. Closed Loop Accelerate

8.4.6.6 Control Coefficient

The DRV10983-Q1 device continuously measures the motor current and uses this information to control the drive state of the motor when operating in closed-loop mode. In applications where noise makes it difficult to control the commutation optimally, the CtrlCoef[1:0] can be used to attenuate the feedback used for closed-loop control. The loop is less reactive to the noise on the feedback and provides for a smoother output.

8.4.6.7 Commutation Control Advance Angle

To achieve the best efficiency, it is often desirable to control the drive state of the motor so that the motor phase current is aligned with the motor BEMF voltage.

To align the motor phase current with the motor BEMF voltage, consider the inductive effect of the motor. The voltage applied to the motor should be applied in advance of the motor BEMF voltage (see Figure 27). The DRV10983-Q1 device provides configuration bits for controlling the time (t_adv) between the driving voltage and BEMF.

For motors with salient pole structures, aligning the motor BEMF voltage with the motor current may not achieve the best efficiency. In these applications, the timing advance should be adjusted accordingly. Accomplish this by operating the system at constant speed and load conditions and by adjusting t_adv until the minimum current is achieved.

Figure 27. Advance Time (t_adv) Definition

The DRV10983-Q1 device has two options for adjusting the motor commutate advance time. When CommAdvMode = 0, mode 0 is selected. When CommAdvMode = 1, mode 1 is selected.

Mode 0: t_adv is maintained to be a fixed time relative to the estimated BEMF zero cross as determined by Equation 5.

Mode 1: t_adv is maintained to be a variable time relative to the estimated BEMF zero cross as determined by Equation 6.

t_SETTING (in µs) is determined by the configuration of the TCtrlAdvShift [2:0] and TCtrlAdvValue [3:0] bits as defined in Equation 7. For convenience, the available t_SETTING values are provided in Table 6.

Table 7. DRV10983-Q1 Current-Limit Modes

8.4.7.1 Acceleration Current Limit

The acceleration current limit limits the voltage applied to the motor to prevent the current from exceeding the programmed threshold. The acceleration current limit threshold is configured by writing the SWiLimitThr[3:0] bits to select I_LIMIT. The acceleration current limit does not use a direct measurement of current. It uses the programmed motor resistance, Rm, and programmed motor velocity constant, Kt, to limit the voltage applied to the motor, U, as shown in Figure 28 and Equation 8.

When the acceleration current limit is active, it does not stop the motor from spinning nor does it trigger a fault. The functionality of the acceleration current limit is only available in closed-loop control.

Figure 28. Acceleration Current Limit

8.4.8.1 Lock0: Lock-Detection Current Limit Triggered

The lock-detection current-limit function provides a configurable threshold for limiting the current to prevent damage to the system. This is often tripped in the event of a sudden locked-rotor condition. The DRV10983-Q1 device continuously monitors the current in the low-side drivers as shown in Figure 30. If the current goes higher than the threshold configured by the HWiLimitThr[2:0] bits, then the DRV10983-Q1 device stops driving the motor by placing the output phases into a high-impedance state. The Lock0 bit is set and a lock condition is reported. It retries after t_{LOCK_OFF}.

Set the lock-detection current limit to a higher value than the acceleration current limit.

Figure 30. Lock-Detection Current Limit

8.4.8.2 Lock1: Abnormal Speed

If the motor is operating normally, the motor BEMF should always be less than the output amplitude. The DRV10983-Q1 device uses two methods of monitoring the BEMF in the system. The U phase current is monitored to maintain an estimate of BEMF based on the setting for Rm[6:0] {RmShift[2:0],RmValue[3:0]}. In addition, the BEMF is estimated based on the operation speed of the motor and the setting for Kt[6:0] {KtShift[2:0],KtValue[3:0]}. Figure 31 shows the method for using this information to detect a lock condition. If the motor BEMF is much higher than the output amplitude for a certain period of time, t_{LCK_ETR}, it means the estimated speed is wrong, and the motor has gotten out of phase.

Figure 31. Lock Detection 1

8.4.8.3 Lock2: Abnormal Kt

For any given motor, the integrated value of BEMF during half of an electrical cycle is constant. The value is determined by the motor velocity constant (Kt_PH) (see Figure 32). The motor velocity constant is the same regardless of whether the motor is running fast or slow. This constant value is continuously monitored by calculation and used as a criterion to determine the motor lock condition, and is referred to as Ktc.

Based on the Kt_PH value programmed, create a range from Kt_low to Kt_high. If Ktc goes beyond the range for a certain period of time, t_{LCK_ETR}, lock is detected. Kt_low and Kt_high are determined by KtLckThr[1:0] (see Figure 33).

Figure 32. BEMF Integration

Figure 33. Abnormal-Kt Lock Detect

8.4.8.4 Lock3 (Fault3): No-Motor Fault

The phase U current is checked after transitioning from open loop to closed loop. If phase U current is not greater than 140 mA then the motor is not connected as shown in Figure 34. This condition is treated and reported as a fault.

Figure 34. No Motor Error

8.4.8.5 Lock4: Open-Loop Motor-Stuck Lock

Lock4 is used to detect locked-motor conditions while the motor start sequence is in open loop.

For a successful startup, motor speed should be equal to the open-to-closed-loop handoff threshold when the motor is transitioning into closed loop. However, if the motor is locked, the motor speed is not able to match the open-loop drive rate.

If the motor BEMF is not detected for one electrical cycle after the open-loop drive rate exceeds the threshold, then the open loop was unsuccessful as a result of a locked-rotor condition.

8.4.8.6 Lock5: Closed Loop Motor Stuck Lock

If the motor suddenly becomes locked, motor speed and Ktc are not able to be refreshed because the BEMF zero cross of the motor may not appear after the lock. In this condition, lock can also be detected by the following scheme: if the current commutation period is 2× longer than the previous period.

8.4.9.1 Mechanical AVS Function

If the speed command suddenly drops such that the BEMF voltage generated by the motor is greater than the voltage that is applied to the motor, then the mechanical energy of the motor is returned to the power supply and the V_CC voltage surges. The mechanical AVS function works to prevent this from happening. The DRV10983-Q1 device buffers the speed command value and limits the resulting output voltage, U_MIN, so that it is not less than the BEMF voltage of the motor. The BEMF voltage in the mechanical AVS function is determined using the programmed value for the motor Kt (Kt[6:0]) along with the speed. Figure 35 shows the criteria used by the mechanical AVS function.

Figure 35. Mechanical AVS

The mechanical AVS function can operate in one of two modes, which can be configured by the register bit AVSMMd:

AVSMMd = 0 – AVS mode is always active to prevent the applied voltage from being less than the BEMF voltage.

AVSMMd = 1 – AVS mode becomes active when V_CC reaches 24 V. The motor acts as a generator and returns energy into the power supply until V_CC reaches 24 V. This mode can be used to enable faster deceleration of the motor in applications where returning energy to the power supply is allowed.

8.4.9.2 Inductive AVS Function

When the DRV10983-Q1 device transitions from driving the motor into a high-impedance state, the inductive current in the motor windings continues to flow and the energy returns to the power supply through the intrinsic body diodes in the FET output stage (see Figure 36).

Figure 36. Inductive-Mode Voltage Surge

To prevent the inductive energy from being returned to the power supply, the DRV10983-Q1 system transitions from driving to a high-impedance state by first turning off the active high-side drivers, and then after a fixed period of time (BrkDoneThr[2:0]), turning off the low-side drivers (see Figure 37).

Figure 37. Inductive AVS

In this example, current is applied to the motor through the high-side driver on phase U (S1) and returned through the low-side driver on phase W (S6). The high-side driver on phase U is turned off and after a period of time (to allow the inductive energy in the resulting LR circuit to decay) the low-side driver on phase W is turned off. If BrkDoneThr[2:0] = 000, no brake will be applied and the device will not protect from inductive energy even with the inductive AVS feature enabled.

8.4.11.1 FG Output Frequency

The FG output frequency can be configured by FGcycle[3:0]. The default FG toggles once every electrical cycle (FGcycle = 0000). Many applications configure the FG output so that it provides two pulses for every mechanical rotation of the motor. The configuration bits provided in the DRV10983-Q1 device can accomplish this for 2-pole, 4-pole, 6-pole, and 8-pole motors up to 32-pole motors. This is illustrated in Figure 38 for 2, 4, 6, and 8-pole motors.

Figure 38 shows the DRV10983-Q1 device has been configured to provide FG pulses once every electrical cycle (4 poles), twice every three electrical cycles (6 poles), once every two electrical cycles (8 poles), and once every three electrical cycles (12 poles).

Note that when it is set to two FG pulses every three electrical cycles, the FG output is not 50% duty cycle. Motor speed is able to be measured by monitoring the rising edge of the FG output.

Figure 38. FG Frequency Divider

8.4.11.2 FG Open Loop and Lock Behavior

Note that the FG output reflects the driving state of the motor. During normal closed-loop behavior, the driving state and the actual state of the motor are synchronized. During open-loop acceleration, however, this may not reflect the actual motor speed. During a locked-motor condition, the FG output is driven high.

The DRV10983-Q1 device provides three options for controlling the FG output during open loop, as shown in Figure 39. The selection of these options is determined by the FGOLSel[1:0] setting.

• Option0: Open-loop, FG output based on driving frequency
• Option1: Open-loop, no FG output (keep high)
• Option2: FG output based on driving frequency at the first power-on startup, and no FG output (keep high) for any subsequent restarts

Figure 39. FG Behavior During Open Loop

8.4.12.1 Motor-Status Readback

The motor FaultReg register provides information on overtemperature (OverTemp), overcurrent (OverCurr), and locked rotor (Lock0–Lock5).

8.4.12.2 Motor-Speed Readback

The motor operation speed is automatically updated in register MotorSpeed while the motor is spinning. The value is determined by the period for calculated BEMF zero crossings on phase U. The electrical speed of the motor is denoted as Velocity (Hz) and is calculated as shown in Equation 9.

As an example consider the following:

MotorSpeed = 0x01FF;

Velocity = 512 (0x01FF) / 10 = 51 Hz

For a 4-pole motor, this translates to:

8.4.12.3 Motor Electrical-Period Readback

The motor-operation electrical period is automatically updated in register MotorPeriod while the motor is spinning. The electrical period is measured as the time between calculated BEMF zero crossings for phase U. The electrical period of the motor is denoted as t_{ELE_PERIOD} (µs) and is calculated as shown in Equation 10.

As an example consider the following:

MotorPeriod = 0x01FF;

t_{ELE_PERIOD} = 512 (0x01FF) × 10 = 5120 µs

The motor electrical period and motor speed satisfies the condition of Equation 11.

8.4.12.4 Motor Velocity Constant Read Back

For any given motor, the integrated value of BEMF during half of an electronic cycle is a constant, Ktc (see Lock2: Abnormal Kt ).

The integration of the motor BEMF is processed periodically (updated every electrical cycle) while the motor is spinning. The result is stored in register MotorKt.

The relationship is shown in .

8.4.12.5 Motor Estimated Position by IPD

After inductive sense is executed, the rotor position is detected within 60 electrical degrees of resolution. The position is stored in register IPDPosition.

The value stored in IPDPosition corresponds to one of the six motor positions plus the IPD advance angle as shown in Table 8. For more information about IPD, see IPD.

Table 8. IPD Position Read Back

Rotor position (°)	0	60	120	180	240	300
Data1	0	43	85	128	171	213
IPD advance angle	30	60	90	120
Data2	22	44	63	85
Register data	(Data1 + Data2) mod (256)

8.4.12.6 Supply-Voltage Readback

The power supply is monitored periodically during motor operation. This information is available in register SupplyVoltage. The power supply voltage is recorded as shown in Equation 13.

8.4.12.7 Speed-Command Readback

The DRV10983-Q1 device converts the various types of speed command into a speed command value (SpeedCmd) as shown in Figure 40. By reading SpeedCmd, the user can observe PWM input duty (PWM digital mode), analog voltage (analog mode), or I²C data (I²C mode). This value is calculated as shown in Equation 14.

Equation 14 shows how the speed command as a percentage can be calculated and set in SpeedCmd.

8.4.12.8 Speed-Command Buffer Readback

If acceleration current limit and AVS are enabled, the PWM duty cycle output (read back at spdCmdBuffer) may not always match the input command (read back at SpeedCmd) shown in Figure 40. See Anti Voltage Supression Function and Current Limit.

By reading the value of spdCmdBuffer, the user can observe buffered speed command (output PWM duty cycle) to the motor.

Equation 15 shows how the buffered speed is calculated.

Figure 40. SpeedCmd and spdCmdBuffer Registers

8.4.12.9 Fault Diagnostics

See Lock Detect and Fault Handling.

Table 9. Default EEPROM Values

Table 10. Access Type Codes

8.5.3.1 FaultReg Register (address = 0x00) [reset = 0x00]

8.5.3.2 MotorSpeed Register (address = 0x01) [reset = 0x00]

8.5.3.3 MotorPeriod Register (address = 0x02) [reset = 0x00]

8.5.3.4 MotorKt Register (address = 0x03) [reset = 0x00]

8.5.3.5 MotorCurrent Register (address = 0x04) [reset = 0x00]

8.5.3.6 IPDPosition–SupplyVoltage Register (address = 0x05) [reset = 0x00]

8.5.3.7 SpeedCmd–spdCmdBuffer Register (address = 0x06) [reset = 0x00]

8.5.3.8 AnalogInLvl Register (address = 0x07) [reset = 0x00]

8.5.3.9 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]

8.5.3.10 DeviceID–RevisionID Register (address = 0x08) [reset = 0x00]

8.5.3.11 Unused Registers (addresses = 0x011 Through 0x2F)

Registers 0x09 through 0x2F are not used.

8.5.3.12 SpeedCtrl Register (address = 0x30) [reset = 0x00]

8.5.3.13 EEPROM Programming1 Register (address = 0x31) [reset = 0x00]

8.5.3.14 EEPROM Programming2 Register (address = 0x32) [reset = 0x00]

8.5.3.15 EEPROM Programming3 Register (address = 0x33) [reset = 0x00]

8.5.3.16 EEPROM Programming4 Register (address = 0x34) [reset = 0x00]

8.5.3.17 EEPROM Programming5 Register (address = 0xYY) [reset = 0x00]

8.5.3.18 EEPROM Programming6 Register (address = 0x36) [reset = 0x00]

8.5.3.19 Unused Registers (addresses = 0x37 Through 0x5F)

Registers 0x37 through 0x5F are not used.

8.5.3.20 EECTRL Register (address = 0x60) [reset = 0x00]

8.5.3.21 Unused Registers (addresses = 0x61 Through 0x8F)

Registers 0x61 through 0x8F are not used.

8.5.3.22 CONFIG1 Register (address = 0x90) [reset = 0x00]

8.5.3.23 CONFIG2 Register (address = 0x91) [reset = 0x00]

8.5.3.24 CONFIG3 Register (address = 0x92) [reset = 0x00]

8.5.3.25 CONFIG4 Register (address = 0x93) [reset = 0x00]

8.5.3.26 CONFIG5 Register (address = 0x94) [reset = 0x00]

8.5.3.27 CONFIG6 Register (address = 0x95) [reset = 0x00]

8.5.3.28 CONFIG7 Register (address = 0x96) [reset = 0x00]