SNLS144K June   2005  – March 2024 DS40MB200

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Ratings
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Switching Characteristics
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 CML Inputs and EQ
      2. 7.3.2 Multiplexer and Loopback Control
      3. 7.3.3 CML Drivers and Pre-Emphasis Control
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 Support Resources
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information

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4 Pin Configuration and Functions

DS40MB200 NJU Package48-Pin WQFNTop View Figure 4-1 NJU Package48-Pin WQFNTop View
Table 4-1 Pin Functions
PIN I/O(1) DESCRIPTION(2)
NAME NO.
LINE-SIDE HIGH-SPEED DIFFERENTIAL I/Os
LI_0+
LI_0−		 6
7		 I Inverting and noninverting differential inputs of port_0 at the line side. LI_0+ and LI_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1.
LI_1+
LI_1−		 30
31		 I Inverting and noninverting differential inputs of port_1 at the line side. LI_1+ and LI_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1.
LO_0+
LO_0−		 33
34		 O Inverting and noninverting differential outputs of port_0 at the line side. LO_0+ and LO_0− have an internal 50 Ω connected to VCC.
LO_1+
LO_1−		 9
10		 O Inverting and noninverting differential outputs of port_1 at the line side. LO_1+ and LO_1− have an internal 50 Ω connected to VCC.
SWITCH-SIDE HIGH SPEED-DIFFERENTIAL I/Os
SIA_0+
SIA_0−		 40
39		 I Inverting and noninverting differential inputs to the mux_0 at the switch_A side. SIA_0+ and SIA_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1.
SIA_1+
SIA_1−		 16
15		 I Inverting and noninverting differential inputs to the mux_1 at the switch_A side. SIA_1+ and SIA_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1.
SIB_0+
SIB_0−		 43
42		 I Inverting and noninverting differential inputs to the mux_0 at the switch_B side. SIB_0+ and SIB_0− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1.
SIB_1+
SIB_1−		 19
18		 I Inverting and noninverting differential inputs to the mux_1 at the switch_B side. SIB_1+ and SIB_1− have an internal 50 Ω connected to an internal reference voltage. See Figure 7-1.
SOA_0+
SOA_0−		 46
45		 O Inverting and noninverting differential outputs of mux_0 at the switch_A side. SOA_0+ and SOA_0− have an internal 50 Ω connected to VCC.
SOA_1+
SOA_1−		 22
21		 O Inverting and noninverting differential outputs of mux_1 at the switch_A side. SOA_1+ and SOA_1− have an internal 50 Ω connected to VCC.
SOB_0+
SOB_0−		 4
3		 O Inverting and noninverting differential outputs of mux_0 at the switch_B side. SOB_0+ and SOB_0− have an internal 50 Ω connected to VCC.
SOB_1+
SOB_1−		 28
27		 O Inverting and noninverting differential outputs of mux_1 at the switch_B side. SOB_1+ and SOB_1− have an internal 50 Ω connected to VCC.
CONTROL (3.3-V LVCMOS)
LB0A 47 I A logic low at LB0A enables the internal loopback path from SIA_0± to SOA_0±. LB0A is internally pulled high.
LB0B 48 I A logic low at LB0B enables the internal loopback path from SIB_0± to SOB_0±. LB0B is internally pulled high.
LB1A 23 I A logic low at LB1A enables the internal loopback path from SIA_1± to SOA_1±. LB1A is internally pulled high.
LB1B 24 I A logic low at LB1B enables the internal loopback path from SIB_1± to SOB_1±. LB1B is internally pulled high.
MUX_S0 37 I A logic low at MUX_S0 selects mux_0 to switch B. MUX_S0 is internally pulled high. Default state for mux_0 is switch A.
MUX_S1 13 I A logic low at MUX_S1 selects mux_1 to switch B. MUX_S1 is internally pulled high. Default state for mux_1 is switch A.
PREL_0
PREL_1		 12
1		 I PREL_0 and PREL_1 select the output pre-emphasis of the line side drivers (LO_0± and LO_1±). PREL_0 and PREL_1 are internally pulled high. See Table 7-3 for line side pre-emphasis levels.
PRES_0
PRES_1		 36
25		 I PRES_0 and PRES_1 select the output pre-emphasis of the switch side drivers (SOA_0±, SOB_0±, SOA_1± and SOB_1±). PRES_0 and PRES_1 are internally pulled high. See Table 7-4 for switch side pre-emphasis levels.
RSV 26 I Reserve pin to support factory testing. This pin can be left open, or tied to GND, or tied to GND through an external pull-down resistor.
POWER
GND 5, 11, 17, 32, 41 P Ground reference. Each ground pin must be connected to the ground plane through a low inductance path, typically with a via located as close as possible to the landing pad of the GND pin.
GND DAP P Die Attach Pad (DAP) is the metal contact at the bottom side, located at the center of the WQFN-48 package. It must be connected to the GND plane with at least 4 via to lower the ground impedance and improve the thermal performance of the package.
VCC 2, 8, 14, 20, 29, 35, 38, 44 P VCC = 3.3 V ± 5%.
Each VCC pin must be connected to the VCC plane through a low inductance path, typically with a via located as close as possible to the landing pad of the VCC pin.
TI recommends to have a 0.01 μF or 0.1 μF, X7R, size-0402 bypass capacitor from each VCC pin to ground plane.
(1) I = Input, O = Output, P = Power
(2) All CML Inputs or Outputs must be AC coupled.