JAJSLU0A June   2023  – February 2024 ISO1228

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Surge Protection
      2. 7.3.2  Field Side LED Indication
      3. 7.3.3  Serial and Parallel Output option
      4. 7.3.4  Cyclic Redundancy Check (CRC)
      5. 7.3.5  FAULT Indication
      6. 7.3.6  Digital Low Pass Filter
      7. 7.3.7  SPI Register Map
      8. 7.3.8  SPI Interface Timing - Non-Daisy Chain
      9. 7.3.9  SPI Interface Timing - Daisy Chain
      10. 7.3.10 SPI Interface Timing - Burst Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Type Digital Inputs
      2. 8.2.2 Sourcing Type Digital Inputs
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
          1. 8.2.3.1.1 Current Limit
          2. 8.2.3.1.2 Voltage Thresholds
          3. 8.2.3.1.3 Wire-Break Detection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.10 SPI Interface Timing - Burst Mode

ISO1228 device supports Burst mode SPI operation if the pin BRST=HIGH. In this mode, the outputs of the three SPI read-only registers Reg0, Reg1 and Reg2 are shifted out continuously in a circular manner on every CS toggle. The timing for this mode is shown in Figure 7-6. This mode is suitable for applications that do not want to provide address information through SDI, but want to read out information from Reg0, Reg1 and Reg2. When BRST pin is toggled, the device needs a RESET to update the mode.
GUID-20220124-SS0I-8BF7-XRK4-2ZHCXQFB5NJ7-low.svg Figure 7-6 SPI Burst Mode Timing Block Diagram.

Burst mode operation is also supported in Daisy Chain configuration. On the first CS toggle, the Reg0 information from all devices in the Daisy Chain is read out. On the next CS toggle, Reg1 information from all the devices is read out. On the next CS toggle, Reg2 information, and then back to Reg0 information. The OUT8/SYNC pin is asserted HIGH when Reg0 information is being transmitted for synchronization with the MCU. The timing for Burst mode in Daisy Chain is shown in Figure 7-7. Note that for simplicity the read out of only Reg0 and Reg1 is shown, and with only two devices in the Daisy Chain.

GUID-20220124-SS0I-XCXC-MNJ1-VKWDDKCCS07Q-low.svg Figure 7-7 SPI Burst Mode Timing Diagram in Daisy Chain .