JAJSLU0A June   2023  – February 2024 ISO1228

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics—DC Specification
    10. 5.10 Switching Characteristics—AC Specification
    11. 5.11 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Test Circuits
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Surge Protection
      2. 7.3.2  Field Side LED Indication
      3. 7.3.3  Serial and Parallel Output option
      4. 7.3.4  Cyclic Redundancy Check (CRC)
      5. 7.3.5  FAULT Indication
      6. 7.3.6  Digital Low Pass Filter
      7. 7.3.7  SPI Register Map
      8. 7.3.8  SPI Interface Timing - Non-Daisy Chain
      9. 7.3.9  SPI Interface Timing - Daisy Chain
      10. 7.3.10 SPI Interface Timing - Burst Mode
    4. 7.4 Device Functional Modes
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Sinking Type Digital Inputs
      2. 8.2.2 Sourcing Type Digital Inputs
      3. 8.2.3 Design Requirements
        1. 8.2.3.1 Detailed Design Procedure
          1. 8.2.3.1.1 Current Limit
          2. 8.2.3.1.2 Voltage Thresholds
          3. 8.2.3.1.3 Wire-Break Detection
  10. 9 Power Supply Recommendations
  11. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  12. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 静電気放電に関する注意事項
    6. 11.6 用語集
  13. 12Revision History
  14. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Tape and Reel Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

4 Pin Configuration and Functions

GUID-20230303-SS0I-BDVZ-7L47-4DSF01DLSLBD-low.svg Figure 4-1 ISO1228
Table 4-1 Pin Functions—38 Pins
PIN I/O DESCRIPTION
NO. NAME
1 IN1 I/O Field Input, Channel 1
2 LED1 I/O LED Indication Pin, Channel 1
3 IN2 I/O Field Input, Channel 2
4 LED2 I/O LED Indication Pin, Channel 2
5 IN3 I/O Field Input, Channel 3
6 LED3 I/O LED Indication Pin, Channel 3
7 AVSS — Field Side Negative Supply
8 IN4 I/O Field Input, Channel 4
9 LED4 I/O LED Indication Pin, Channel 4
10 IN5 I/O Field Input, Channel 5
11 LED5 I/O LED Indication Pin, Channel 5
12 IN6 I/O Field Input, Channel 6
13 LED6 I/O LED Indication Pin, Channel 6
14 IN7 I/O Field Input, Channel 7
15 LED7 I/O LED Indication Pin, Channel 7
16 AVCC — Field Side Power Supply
17 AVSS — Field Side Negative Supply
18 IN8 I/O Field Input, Channel 8
19 LED8 I/O LED Indication Pin, Channel 8
20 NC — Leave unconnected
21 GND1 — Logic Ground
22 NC — Leave unconnected
23 F1 I Digital Filter Setting
24 F0 I Digital Filter Setting
25 GND1 — Logic Ground
26 nFAULT O Open Drain Ouput. Connect 4.7 kΩ pull-up to VCC1
27 OUT_EN I Ouput Enable. Output pins OUT1 through OUT8 are tri-stated if OUT_EN=0 or FLOAT
28 OUT8/SYNC O Synchronize data in Burst Mode(COMM_SEL=VCC1)

Data Output, Channel 8, in Parallel Interface Mode (COMM_SEL=0)
29 OUT7/BURST_EN I/O Burst Mode in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 7, in Parallel Interface Mode (COMM_SEL=0)
30 OUT6/nRST I/O Active Low SPI Reset in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 6, in Parallel Interface Mode (COMM_SEL=0)
31 OUT5/nINT O Active Low SPI Interrupt in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 5, in Parallel Interface Mode (COMM_SEL=0)
32 OUT4/nCS I/O SPI Chip Seltect in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 4, in Parallel Interface Mode (COMM_SEL=0)
33 OUT3/SCLK I/O SPI Clock in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 3, in Parallel Interface Mode (COMM_SEL=0)
34 OUT2/SDI I/O SPI Input Data in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 2, in Parallel Interface Mode (COMM_SEL=0)
35 OUT1/SDO O SPI Output Data in Serial Interface Mode (COMM_SEL=VCC1)

Data Output, Channel 1, in Parallel Interface Mode (COMM_SEL=0)
36 GND1 — Logic Ground
37 VCC1 — Logic Supply
38 COMM_SEL I Serial vs. Parallel Interface selection

Serial Interface Mode if COMM_SEL=VCC1

Parallel Interface Mode if COMM_SEL=0 or Floating
  • I = Input, O = Output, I/O = Input/Output
  • Connect all AVSS pins on Field side together
  • Connect all GND1 pins on backplane/MCU side together