12.1 Layout Guidelines

A minimum of four layers is required to accomplish a low-EMI PCB design (see Figure 35). Layer stacking should be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane, and low-frequency signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits of the data link.
• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for transmission line interconnects and provides an excellent low-inductance path for the return current flow.
• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of approximately 100 pF/in².
• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links usually have margin to tolerate discontinuities such as vias.
• Keep decoupling capacitors as close as possible to the V_CC and V_ISO pins.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system to the stack to keep it symmetrical. This makes the stack mechanically stable and prevents it from warping. Also the power and ground plane of each power system can be placed closer together, thus increasing the high-frequency bypass capacitance significantly.

Because the device has no thermal pad to dissipate heat, the device dissipates heat through the respective GND pins. Ensure that enough copper is present on both GND pins to prevent the internal junction temperature of the device from rising to unacceptable levels.

The ISOW7821 integrated signal and power isolation device simplifies system design and reduces board area. The use of low-inductance micro-transformers in the ISOW7821 device necessitates the use of high frequency switching, resulting in higher radiated emissions compared to discrete solutions. The ISOW7821 device uses on-chip circuit techniques to reduce emissions compared to competing solutions. For further reduction in radiated emissions at system level, refer to the Low-Emission Designs With ISOW7841 Integrated Signal and Power Isolator application report.