JAJSNC5 april 2023 LM5171-Q1
ADVANCE INFORMATION
The SS pin also fulfills the function of a restart timer in an OVP event or following a DIR command change:
(1) Restart Timer in OVP: When OVP catches an overvoltage event (refer to Section 7.3.16), CSS1 of CH-1 is discharged immediately by the internal pulldown FET, and this FET remains ON as long as the overvoltage condition persists. When the overvoltage condition is removed and after the SS/DEM1 voltage is discharged to below 0.3 V, the pulldown is released, setting off a new soft-start cycle. The circuit may run in retry or hiccup mode if the overvoltage condition reappears. The retry frequency is determined by the CSS1 as well as the nature of the overvoltage condition.
Note that OVP only affects SS/DEM1 but not SS/DEM2. For multiphase parallel operation, connect SS/DEM1 and SS/DEM2 to enable the same hiccup mode in CH-2 as shown in Figure 7-12. For independent channel operation, an external OVP protection circuit is needed for CH-2, and that circuit must be configured to discharge SS/DEM2 to achieve OVP and also the hiccup mode operation. Figure 7-19 shows an example of such an external OVP implementation for CH-2. See Figure 7-22 and Figure 7-23 for other examples.
(2) Restart Timer after a DIR Change: When DIR dynamically flips its state from 0 to 1, or 1 to 0 during operation, CSS is first discharged to 0.3 V by the internal pulldown FET, then the pulldown is released to set off a new soft-start cycle to gradually build up the channel current in the new direction. In this way, the channel current overshoot is eliminated.
For independent channel operation, DIR1 and DIR2 can be independently controlled. For multiphase parallel operation, DIR1 and DIR2 must be tied together, and the user may also consider tying the SS/DEM1 and SS/DEM2 together.