JAJSNC5 april   2023 LM5171-Q1

ADVANCE INFORMATION  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Bias Supplies and Voltage Reference (VCC, VDD, and VREF)
      2. 7.3.2  Undervoltage Lockout (UVLO) and Controller Enable or Disable
      3. 7.3.3  High Voltage Inputs (HV1, HV2)
      4. 7.3.4  Current Sense Amplifier
      5. 7.3.5  Control Commands
        1. 7.3.5.1 Channel Enable Commands (EN1, EN2)
        2. 7.3.5.2 Direction Command (DIR1 and DIR2)
        3. 7.3.5.3 Channel Current Setting Commands (ISET1 and ISET2)
      6. 7.3.6  Channel Current Monitor (IMON1, IMON2)
        1. 7.3.6.1 Individual Channel Current Monitor
        2. 7.3.6.2 Multiphase Total Current Monitoring
      7. 7.3.7  Cycle-by-Cycle Peak Current Limit (IPK)
      8. 7.3.8  Inner Current Loop Error Amplifier
      9. 7.3.9  Outer Voltage Loop Error Amplifier
      10. 7.3.10 Soft Start, Diode Emulation, and Forced PWM Control (SS/DEM1 and SS/DEM2)
        1. 7.3.10.1 Soft-Start Control by the SS/DEM Pins
        2. 7.3.10.2 DEM Programming
        3. 7.3.10.3 FPWM Programming and Dynamic FPWM and DEM Change
        4. 7.3.10.4 SS Pin as the Restart Timer
      11. 7.3.11 Gate Drive Outputs, Dead Time Programming and Adaptive Dead Time (HO1, HO2, LO1, LO2, DT/SD)
      12. 7.3.12 Emergent Latched Shutdown (DT/SD)
      13. 7.3.13 PWM Comparator
      14. 7.3.14 Oscillator (OSC)
      15. 7.3.15 Synchronization to an External Clock (SYNCI, SYNCO)
      16. 7.3.16 Overvoltage Protection (OVP)
      17. 7.3.17 Multiphase Configurations (SYNCO, OPT)
        1. 7.3.17.1 Multiphase in Star Configuration
        2. 7.3.17.2 Daisy-Chain Configurations for 2, 3, or 4 Phases parallel operations
        3. 7.3.17.3 Daisy-Chain configuration for 6 or 8 phases parallel operation
      18. 7.3.18 Thermal Shutdown
    4. 7.4 Programming
      1. 7.4.1 Dynamic Dead Time Adjustment
      2. 7.4.2 UVLO Programming
    5. 7.5 I2C Serial Interface
      1. 7.5.1 REGFIELD Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Small Signal Model
        1. 8.1.1.1 Current Loop Small Signal Model
        2. 8.1.1.2 Current Loop Compensation
        3. 8.1.1.3 Voltage Loop Small Signal Model
        4. 8.1.1.4 Voltage Loop Compensation
    2. 8.2 Typical Application
      1. 8.2.1 60-A, Dual-Phase, 48-V to 12-V Bidirectional Converter
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1  Determining the Duty Cycle
          2. 8.2.1.2.2  Oscillator Programming
          3. 8.2.1.2.3  Power Inductor, RMS and Peak Currents
          4. 8.2.1.2.4  Current Sense (RCS)
          5. 8.2.1.2.5  Current Setting Limits (ISETx)
          6. 8.2.1.2.6  Peak Current Limit
          7. 8.2.1.2.7  Power MOSFETS
          8. 8.2.1.2.8  Bias Supply
          9. 8.2.1.2.9  Boot Strap
          10. 8.2.1.2.10 OVP
          11. 8.2.1.2.11 Dead Time
          12. 8.2.1.2.12 Channel Current Monitor (IMONx)
          13. 8.2.1.2.13 UVLO Pin Usage
          14. 8.2.1.2.14 HVx Pin Configuration
          15. 8.2.1.2.15 Loop Compensation
          16. 8.2.1.2.16 Soft Start
          17. 8.2.1.2.17 PWM to ISET Pins
        3. 8.2.1.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  9. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Development Support
    2. 9.2 ドキュメントの更新通知を受け取る方法
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 静電気放電に関する注意事項
    6. 9.6 用語集
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.6.1 Individual Channel Current Monitor

When the monitors are set to monitor the inductor dc current, which is the input current in the boost mode, or the load current in the buck mode, the monitor current source is determined by Equation 6 and Equation 7:

Equation 6. IMON1 =VCS1500Ω+50μA
Equation 7. IMON2 =VCS2500Ω+50μA

Where

  • VCS1 and VCS2 are the real time current sense voltage of CH-1 and CH-2, respectively.
  • the 50 µA is a DC offset current superimposed on to the IMON signals (refer to Figure 7-5).
GUID-20230329-SS0I-5DP2-7QDR-JCK7MXXX3RPR-low.svg Figure 7-5 IMON Current Source vs Current Sense Voltage

The 50 µA DC offset current is introduced to raise the no-load signal above the possible ground noise floor. Because the monitor signal is in the form of current, an accurate reading can be obtained across a termination resistor even if the resistor is located far from the LM5171-Q1 but close to the MCU, thus rejecting potential ground differences between the LM5171-Q1 and the MCU. Figure 7-9 shows a typical channel current monitor through a 20-KΩ termination resistor and a 10-nF to 100-nF ceramic capacitor in parallel. The RC network converts the current monitor signal into a DC voltage proportional to the channel DC current. For example, when the current sense voltage DC component is 50 mVdc, namely VCS_dc = 50 mV, the termination RC network produces a DC voltage of 3 V. Note that the maximum active operating voltage of the IMON pin is 3 V.

When the monitors are set to monitor the output DC current, which is the channel load current flowing out of the LV-port in the buck mode, or flowing out of the HV-port in the boost mode, the monitor current source is determined by Equation 8 through Equation 11:

Equation 8. IMON1BK =RCS1×IO1_BKRIMON1+50μA
Equation 9. IMON2BK=RCS2×IO2_BKRIMON2+50μA
Equation 10. IMON1BST =RCS1×IO1_BSTRIMON1+50μA
Equation 11. IMON2BST=RCS2×IO2_BSTRIMON2+50μA

Where

  • IO1_BK and IO2_BK are the buck mode load current of CH-1 and CH-2, respectively.
  • IO1_BST and IO2_BST are the boost mode load current of CH-1 and CH-2, respectively.

Obviously, the buck mode channel load current is the same as shown in Figure 7-5. However, the boost load current can be shown as in Figure 7-6.

GUID-20230329-SS0I-4Z2W-DBCK-JKFD98MTBH7C-low.svg Figure 7-6 IMON Current Source vs Boost Load Current
GUID-20230329-SS0I-NGJF-T9R7-PRRCCVH0QTXJ-low.svg Figure 7-7 Channel Current Monitor